Merge "feat(rockchip): update uart baudrate for rk3399" into integration

feat(rk3576): support rk3576

rk3576 is an Octa-core soc with Cortex-a53/a72 inside.
This patch supports the following functions:
1. basic platform setup
2. power up/off cpus
3. suspend/resume cpus
4

feat(rk3576): support rk3576

rk3576 is an Octa-core soc with Cortex-a53/a72 inside.
This patch supports the following functions:
1. basic platform setup
2. power up/off cpus
3. suspend/resume cpus
4. suspend/resume system
5. reset system
6. power off system

Change-Id: I67a019822bd4af13e4a3cdd09cf06202f4922cc4
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>

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Merge "fix(rme): map DEVICE0_BASE as EL3_PAS" into integration

Merge changes from topic "versal2-pm-support" into integration

* changes:
feat(versal2): extended SMCCC payload for EEMI
feat(versal2): add support for platform management
feat(versal2): add d

Merge changes from topic "versal2-pm-support" into integration

* changes:
feat(versal2): extended SMCCC payload for EEMI
feat(versal2): add support for platform management
feat(versal2): add dependency macro for PM

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feat(versal2): extended SMCCC payload for EEMI

Until Versal, the extended SMCCC payload was supported only for
QUERY_DATA, while other APIs used the legacy SMCCC format.

In Versal Gen 2, all EEMI A

feat(versal2): extended SMCCC payload for EEMI

Until Versal, the extended SMCCC payload was supported only for
QUERY_DATA, while other APIs used the legacy SMCCC format.

In Versal Gen 2, all EEMI APIs are supported with extended SMCCC
payload only, enabling a simplified and efficient pass-through
implementation.

Also, set TFA_NO_PM to 0 to enable power management by default.

Change-Id: I937be3c78ebe87c62f8697a0a82cdcd21c185f56
Signed-off-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com>

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feat(versal2): add support for platform management

Add support for PM functionality through EEMI interface for
Versal Gen 2. Add support of PM APIs in PSCI ops. Add
TFA_NO_PM flag to disable PM func

feat(versal2): add support for platform management

Add support for PM functionality through EEMI interface for
Versal Gen 2. Add support of PM APIs in PSCI ops. Add
TFA_NO_PM flag to disable PM functionality. Enable wakeup for
new peripherals

Change-Id: I1bf67dc46af91ee113c627d32ae6ecc1dad386c2
Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>
Signed-off-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com>

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fix(rmm): add support for BRBCR_EL2 register for feat_brbe

Currently BRBE is being disabled for Realm world in EL3 by
switching the SBRBE bit in mdcr_el3 register to 0b00.
The patch removes the swit

fix(rmm): add support for BRBCR_EL2 register for feat_brbe

Currently BRBE is being disabled for Realm world in EL3 by
switching the SBRBE bit in mdcr_el3 register to 0b00.
The patch removes the switching of SBRBE bits, and adds
context switch of BRBCR_EL2 register.

Change-Id: I66ca13edefc37e40fa265fd438b0b66f7d09b4bb
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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feat(versal2): add dependency macro for PM

The pm_api_sys.c file has dependency on the PLAT_ARM_GICR_BASE macro.
Add the macro to fix compilation error when PM is enabled.

Change-Id: Ibd77dd38b4a2a

feat(versal2): add dependency macro for PM

The pm_api_sys.c file has dependency on the PLAT_ARM_GICR_BASE macro.
Add the macro to fix compilation error when PM is enabled.

Change-Id: Ibd77dd38b4a2a55614064c4ed0b1096acc658a5c
Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>
Signed-off-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com>

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perf(cpus): inline the cpu_get_rev_var call

Similar to the cpu_rev_var_xy functions, branching far away so early in
the reset sequence incurs significant slowdowns. Inline the function.

Change-Id:

perf(cpus): inline the cpu_get_rev_var call

Similar to the cpu_rev_var_xy functions, branching far away so early in
the reset sequence incurs significant slowdowns. Inline the function.

Change-Id: Ifc349015902cd803e11a1946208141bfe7606b89
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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perf(cpus): inline cpu_rev_var checks

We strive to apply errata as close to reset as possible with as few
things enabled as possible. Importantly, the I-cache will not be
enabled. This means that re

perf(cpus): inline cpu_rev_var checks

We strive to apply errata as close to reset as possible with as few
things enabled as possible. Importantly, the I-cache will not be
enabled. This means that repeated branches to these tiny functions must
be re-fetched all the way from memory each time which has glacial speed.
Cores are allowed to fetch things ahead of time though as long as
execution is fairly linear. So we can trade a little bit of space (3 to
7 instructions per erratum) to keep things linear and not have to go to
memory.

While we're at it, optimise the the cpu_rev_var_{ls, hs, range}
functions to take up less space. Dropping the moves allows for a bit of
assembly magic that produces the same result in 2 and 3 instructions
respectively.

Change-Id: I51608352f23b2244ea7a99e76c10892d257f12bf
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(cpus): register DSU errata with the errata framework's wrappers

The existing DSU errata workarounds hijack the errata framework's inner
workings to register with it. However, that is undesi

refactor(cpus): register DSU errata with the errata framework's wrappers

The existing DSU errata workarounds hijack the errata framework's inner
workings to register with it. However, that is undesirable as any change
to the framework may end up missing these workarounds. So convert the
checks and workarounds to macros and have them included with the
standard wrappers.

The only problem with this is the is_scu_present_in_dsu weak function.
Fortunately, it is only needed for 2 of the errata and only on 3 cores.
So drop it, assuming the default behaviour and have the callers handle
the exception.

Change-Id: Iefa36325804ea093e938f867b9a6f49a6984b8ae
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(simd): fix base register in fpregs_context_*" into integration

Merge changes from topic "jw/gic-lca-support" into integration

* changes:
fix(rdn2): add LCA multichip data for RD-N2-Cfg2
fix(rdv3): add LCA multichip data for RD-V3-Cfg2
feat(gic): add suppo

Merge changes from topic "jw/gic-lca-support" into integration

* changes:
fix(rdn2): add LCA multichip data for RD-N2-Cfg2
fix(rdv3): add LCA multichip data for RD-V3-Cfg2
feat(gic): add support for local chip addressing

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refactor(cpus): convert checker functions to standard helpers

The library check_erratum_ls already incorporates the check. The return
of ERRATA_MISSING is handled in the errata_report.c functions.

refactor(cpus): convert checker functions to standard helpers

The library check_erratum_ls already incorporates the check. The return
of ERRATA_MISSING is handled in the errata_report.c functions.

Change-Id: Ic1dff2bc5235195f7cfce1709cd42467f88b3e4c
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(cpus): convert the Cortex-A65 to use the errata framework

Result was verified by manually stepping through the reset function with
a debugger.

Change-Id: I91cd6111ccf95d6b7ee2364ac2126cb98

refactor(cpus): convert the Cortex-A65 to use the errata framework

Result was verified by manually stepping through the reset function with
a debugger.

Change-Id: I91cd6111ccf95d6b7ee2364ac2126cb98ee4bb15
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(cpus): declare reset errata correctly

The errata in this patch are declared as runtime, but are never called
explicitly. This means that they are never called! Convert them to reset
errata so th

fix(cpus): declare reset errata correctly

The errata in this patch are declared as runtime, but are never called
explicitly. This means that they are never called! Convert them to reset
errata so that they are called at reset. Their SDENs entries have been
checked and confirm that this is how they should be implemented.

Also, drop the the MIDR check on the a57 erratum as it's not needed -
the erratum is already called from a cpu-specific function.

Change-Id: I22c3043ab454ce94b3c122c856e5804bc2ebb18b
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "refactor(cpufeat): add FGT2 and Debugv8p9 to realm state" into integration

fix(build): update clang target for aarch64

With the LLVM toolchain delivered by Arm [1], the target aarch64-elf
which is defaulting to aarch64-unknown-unknown-elf is now unknown.
Replace it with aa

fix(build): update clang target for aarch64

With the LLVM toolchain delivered by Arm [1], the target aarch64-elf
which is defaulting to aarch64-unknown-unknown-elf is now unknown.
Replace it with aarch64-unknown-none-elf.

[1]: https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/tag/release-19.1.5

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I5a0fad1ee29838ef2c3a1bc8ecfba05aacf0a6d6

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Merge "fix(cpus): fix a typo in errata doc" into integration

fix(cpus): fix a typo in errata doc

Commit@af5ae9a73f67dc8c9ed493846d031b052b0f22a0
Adding a Cortex-A720-AE erratum 3699562 has a typo in CPU name
for the errata, it is for Cortex-A720-AE but had in

fix(cpus): fix a typo in errata doc

Commit@af5ae9a73f67dc8c9ed493846d031b052b0f22a0
Adding a Cortex-A720-AE erratum 3699562 has a typo in CPU name
for the errata, it is for Cortex-A720-AE but had incorrectly
mentioned as Cortex-A715_AE.

Change-Id: I2332a3fcaf56a7aaab5a04e3d40428cc746d2d46
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "fix(psci): check if a core is the last one in a requested power level" into integration

refactor(cpufeat): add FGT2 and Debugv8p9 to realm state

Enable FEAT_FGT2 and FEAT_Debugv8p9 in Realm state as well.

Change-Id: Ib9cdde3af328ffdd8718b1ba404265757f2e542b
Signed-off-by: Sona Mathew

refactor(cpufeat): add FGT2 and Debugv8p9 to realm state

Enable FEAT_FGT2 and FEAT_Debugv8p9 in Realm state as well.

Change-Id: Ib9cdde3af328ffdd8718b1ba404265757f2e542b
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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feat(rockchip): increase FDT Buffer for Rockchip Devices

Modify the FDT buffer for Rockchip devices to 384KiB. This is done to
allow us to pass mainline devicetrees with symbols through Arm Trusted

feat(rockchip): increase FDT Buffer for Rockchip Devices

Modify the FDT buffer for Rockchip devices to 384KiB. This is done to
allow us to pass mainline devicetrees with symbols through Arm Trusted
Firmware. 384KiB was chosen as 512KiB is very near the maximum
supported with the current reserved memory. As of kernel version 6.13,
the largest devicetree with symbols enabled is 215KiB, and the largest
Rockchip devicetree with symbols enabled is 176KiB
(rk3588-evb1-v10.dtb).

Change-Id: Iea9343d7a30ee26cad3ee5cc848980a93873ae34
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>

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Merge "feat(qemu): add hob support for qemu platforms" into integration

Merge changes from topic "nxp-clk/add_usdhc_clock" into integration

* changes:
feat(s32g274a): enable sdhc clock
feat(nxp-clk): add clock modules for uSDHC
feat(nxp-clk): get MC_CGM divider's

Merge changes from topic "nxp-clk/add_usdhc_clock" into integration

* changes:
feat(s32g274a): enable sdhc clock
feat(nxp-clk): add clock modules for uSDHC
feat(nxp-clk): get MC_CGM divider's parent
feat(nxp-clk): get MC_CGM divider's rate
feat(nxp-clk): set MC_CGM divider's rate
feat(nxp-clk): enable MC_CGM dividers
feat(nxp-clk): get parent for the fixed dividers
feat(nxp-clk): set the rate for partition objects
feat(nxp-clk): add clock objects for CGM dividers
feat(nxp-clk): add base address for PERIPH_DFS

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