feat(neoverse_rd): deprecate and remove RD-N1-Edge platform variants

deprecate and remove support for RD-N1-Edge and RD-N1-Edgex2 platform
variants.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.co

feat(neoverse_rd): deprecate and remove RD-N1-Edge platform variants

deprecate and remove support for RD-N1-Edge and RD-N1-Edgex2 platform
variants.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I59dce73b70014b3416d89b0d024d7204356b1b77

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feat(neoverse_rd): deprecate and remove SGI-575 platform

deprecate and remove support for SGI-575 platform.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Iffee2fa8f4faa463c4b4df5911

feat(neoverse_rd): deprecate and remove SGI-575 platform

deprecate and remove support for SGI-575 platform.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Iffee2fa8f4faa463c4b4df591182f72a461c880b

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Merge "feat(stm32mp15-fdts): add Linux Automation GmbH TAC" into integration

Merge "fix(juno): resolve BL2 RAM overflow with RSA+ECDSA in GCC(14.2.1)" into integration

Merge changes from topic "bk/fvp_r" into integration

* changes:
fix(tbbr): remove tbbr_cot_bl1_r64.c
fix(xlat): remove xlat_mpu

Merge changes from topic "ti-am62l-mailbox-psci-base-support" into integration

* changes:
feat(ti): introduce basic support for the AM62L
feat(ti): introduce PSCI Driver for AM62L
feat(ti): ad

Merge changes from topic "ti-am62l-mailbox-psci-base-support" into integration

* changes:
feat(ti): introduce basic support for the AM62L
feat(ti): introduce PSCI Driver for AM62L
feat(ti): add support for TI mailbox driver
refactor(ti): move out k3/common to ti/common
refactor(ti): introduce ti_bl31_setup
refactor(ti): add the sec hdr to the ti sci msg
refactor(ti): rename the k3_sec_proxy_chan_id
refactor(ti): rename the sec_proxy functions
refactor(ti): add top level ti_sci transport layer
refactor(ti): move TI SCI and sec proxy to drivers

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feat(fvp): support AArch32 booting with handoff

Enable AArch32 SP_MIN booting on the FVP platform using Firmware
Handoff. Update plat_arm_sp_min_early_platform_setup() to parse boot
arguments passed

feat(fvp): support AArch32 booting with handoff

Enable AArch32 SP_MIN booting on the FVP platform using Firmware
Handoff. Update plat_arm_sp_min_early_platform_setup() to parse boot
arguments passed via the Firmware Handoff framework.

Also, adjust the maximum BL32 size calculation to use
PLAT_ARM_FW_HANDOFF_SIZE when TRANSFER_LIST is enabled.

Change-Id: I82032b1cebf8b37ff24dde4f2d07f7aaede33eb6
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(arm): support AArch32 booting with handoff

Configre SP-MIN to receive information via the firmare handoff
framework. In BL1 and BL2, select the 32-bit variants of the SRAM layout
and entry poin

feat(arm): support AArch32 booting with handoff

Configre SP-MIN to receive information via the firmare handoff
framework. In BL1 and BL2, select the 32-bit variants of the SRAM layout
and entry point info to enable booting in aarch32 mode. In SP-MIN
process expected data directly from the transfer list in secure memory.

Change-Id: If0417cdd4c47b772332eb6fd4b71ef0ea474f0fa
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(tbbr): remove tbbr_cot_bl1_r64.c

The only platform to use this is fvp_r. As this platform is now gone, so
is the need for this file. Remove it

Change-Id: If65f1c5f525283e19c8421cfa31498480370b9

fix(tbbr): remove tbbr_cot_bl1_r64.c

The only platform to use this is fvp_r. As this platform is now gone, so
is the need for this file. Remove it

Change-Id: If65f1c5f525283e19c8421cfa31498480370b933
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(xlat): remove xlat_mpu

The only platform to use this is fvp_r. As this platform is now gone, so
is the need for this library. Support for it never went out of
"experimental" so it does not appea

fix(xlat): remove xlat_mpu

The only platform to use this is fvp_r. As this platform is now gone, so
is the need for this library. Support for it never went out of
"experimental" so it does not appear to be finished.

Change-Id: I76499b92ca4368651330f17dc80803991158cc36
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(libc): make sure __init functions are garbage collected

RECLAIM_INIT_CODE is useful to remove code that is only necessary during
boot. However, these functions are generally called once and as s

fix(libc): make sure __init functions are garbage collected

RECLAIM_INIT_CODE is useful to remove code that is only necessary during
boot. However, these functions are generally called once and as such
prime candidates for inlining. When building with LTO, the compiler is
pretty good at inlining every single one, making this option pointless.

So tell the compiler to not inline these functions. This ensures they
are kept separate and they can be garbage collected later. This is
expected to cost a little bit of speed due to the extra branching.

Change-Id: Ie83a9ec8db03cb42139742fc6d728d12ce8549d3
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(platforms): remove platform_core_pos_helper()

Its last user was removed some time ago so it is no longer necessary.

Change-Id: I28264367abd2902ed0d3f207f686538a82a44eba
Signed-off-by: Boyan Kar

fix(platforms): remove platform_core_pos_helper()

Its last user was removed some time ago so it is no longer necessary.

Change-Id: I28264367abd2902ed0d3f207f686538a82a44eba
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "docs: list removal of fvp_r" into integration

Merge "fix(cpus): fix clang compilation issue" into integration

fix(versal-net): enable PSCI reset2 interface

Enable the PSCI reset2 interface for Versal NET. Since warm/soft reset
functionality is not supported in the Versal NET system, the reset2
implementatio

fix(versal-net): enable PSCI reset2 interface

Enable the PSCI reset2 interface for Versal NET. Since warm/soft reset
functionality is not supported in the Versal NET system, the reset2
implementation is aligned with the existing PSCI reset interface.

This implementation allows the external users to define
platform-specific actions for warm/soft reset within the reset2
handler if needed.

Change-Id: Ibb937e4c0994a29b45b9b19f8addad56fe7e7e23
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com>

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feat(stm32mp15-fdts): add Linux Automation GmbH TAC

The Linux Automation Test Automation Controller (LXA TAC)[1] is an embedded
software development tool built around the Octavo Systems OSD32MP15x S

feat(stm32mp15-fdts): add Linux Automation GmbH TAC

The Linux Automation Test Automation Controller (LXA TAC)[1] is an embedded
software development tool built around the Octavo Systems OSD32MP15x SiP.

The device contains an eMMC for storage, a DSA-capable on board ethernet
switch with two external ports, dual CAN busses, a power switch to turn
a device under test on or off and some other I/O.

[1]: https://www.linux-automation.com/en/products/lxa-tac.html

Signed-off-by: Rouven Czerwinski <rouven@czerwinskis.de>
Signed-off-by: Leonard Göhrs <l.goehrs@pengutronix.de>
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
[m.felsch@pengutronix.de: sort phandles alphabetical]
[m.felsch@pengutronix.de: adapt st,pkcs to st,clksrc]
[m.felsch@pengutronix.de: adapt pll vco setup]
[m.felsch@pengutronix.de: adapt commit message]
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: Ic943da379557adba2673064160b85d308d962a29

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fix(cpus): fix clang compilation issue

A potential problem with clang version < 17 can cause resolving nested
'cfi_startproc' to fail compilation.

So add a variant of check_errara/reset_macros that

fix(cpus): fix clang compilation issue

A potential problem with clang version < 17 can cause resolving nested
'cfi_startproc' to fail compilation.

So add a variant of check_errara/reset_macros that is compatible with
clang version < 17 to ignore `cfi_startproc` and `cfi_endproc`.

This wouldn't cause any performance issue and will not affect any
functional behaviour.

Change-Id: I46147af2dd0accd5be14ddb26dea03bb2f87cba8
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge changes I2d140b32,Id59ae926,I31c71551 into integration

* changes:
feat(mt8189): add GPIO support
feat(mt8189): initialize platform for MT8189
refactor(mediatek): move headers to common f

Merge changes I2d140b32,Id59ae926,I31c71551 into integration

* changes:
feat(mt8189): add GPIO support
feat(mt8189): initialize platform for MT8189
refactor(mediatek): move headers to common folder

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docs(build): update GCC toolchain requirement to 14.2.Rel1

Update documentation to reflect the use of GCC version 14.2.Rel1,
the latest production release available at:
https://developer.arm.com/dow

docs(build): update GCC toolchain requirement to 14.2.Rel1

Update documentation to reflect the use of GCC version 14.2.Rel1,
the latest production release available at:
https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads

TF-A is built in CI using x86_64 Linux-hosted cross toolchains:
---------------------------------------------------------------
* AArch32 bare-metal target (arm-none-eabi)
* AArch64 bare-metal target (aarch64-none-elf)

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I4cd2c16fa9daac1ce518d2280169e92562e3766d

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fix(juno): resolve BL2 RAM overflow with RSA+ECDSA in GCC(14.2.1)

* Using "TF_MBEDTLS_RSA_AND_ECDSA" algorithm with toolchain 14.2.1
causes the BL2 image to exceed RAM limits, triggering a link er

fix(juno): resolve BL2 RAM overflow with RSA+ECDSA in GCC(14.2.1)

* Using "TF_MBEDTLS_RSA_AND_ECDSA" algorithm with toolchain 14.2.1
causes the BL2 image to exceed RAM limits, triggering a link error
("region `RAM' overflowed by 4096 bytes").

* Resolved by increasing PLAT_ARM_MAX_BL2_SIZE by 4KB to accommodate
the larger image.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Ie9d411c1207801436d8cffcf72fec2752371eb69

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docs: list removal of fvp_r

Commit 2cadf21bc removed fvp_r but did not list it as such. Do that.

Change-Id: I84e83196add3d0f912fd503cd253bc5496647dd6
Signed-off-by: Boyan Karatotev <boyan.karatotev

docs: list removal of fvp_r

Commit 2cadf21bc removed fvp_r but did not list it as such. Do that.

Change-Id: I84e83196add3d0f912fd503cd253bc5496647dd6
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(plat): remove fvp_r" into integration

fix(smccc): properly set RAS feature bit

The SCR_EL3.TERR bit controls trapping accesses to the RAS CPU system
registers, like ERRIDR_EL1. Those are part of RAS CPU extension, and
exist and can be a

fix(smccc): properly set RAS feature bit

The SCR_EL3.TERR bit controls trapping accesses to the RAS CPU system
registers, like ERRIDR_EL1. Those are part of RAS CPU extension, and
exist and can be accessed independently of the rest of the system's RAS
implementation status, BL31's RAS handling capabilities, or the way RAS
errors are routed by the firmware (FFH vs. KFH handling).
Tie the SCR_EL3.TERR bit to the right build symbol, since TF-A's
capability to handle RAS errors has nothing to do with lower EL's
accesses to those CPU system registers.

Change-Id: I4f06f915c0815c80058ec365139a8d818ba85721
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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fix(trng): allow FEAT_RNG_TRAP in dynamic fashion

The documentation promises for ENABLE_FEAT_RNG_TRAP to support the
numeric semantics, with a value of "2" meaning runtime detection. However
two pla

fix(trng): allow FEAT_RNG_TRAP in dynamic fashion

The documentation promises for ENABLE_FEAT_RNG_TRAP to support the
numeric semantics, with a value of "2" meaning runtime detection. However
two places in the build system did not support this, instead were just
checking for a value of "1".

Fix the AArch32 check and build the FVP specific handler routine when
the value is not "0", instead of relying on it to be exactly "1".

Change-Id: I1acd3ed6d2a461d541b9bf57e4aac9c0798ab56b
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(smccc): add FEAT_TWED to ARCH_FEATURE_AVAILABILITY

FEAT_TWED (Delayed Trapping of WFE) is an ARMv8.6 feature that is
advertised in the ID_AA64MMFR1_EL1 ID register and controlled by a bit
in th

feat(smccc): add FEAT_TWED to ARCH_FEATURE_AVAILABILITY

FEAT_TWED (Delayed Trapping of WFE) is an ARMv8.6 feature that is
advertised in the ID_AA64MMFR1_EL1 ID register and controlled by a bit
in the SCR_EL3 register.

On cores implementing that feature we should announce it in the
ARCH_FEATURE_AVAILABILITY SMCCC call, so that users of that interface
can correctly assess the availability of the delayed trap.

Change-Id: I2b185f7eb9d58e45472983204db0305511372477
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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