Merge pull request #878 from vwadekar/tegra-memctrlv2-coverity-fix

Tegra: memctrl_v2: fix logic to calculate TZRAM_ADDR_HI bits

Add support to change xlat_tables to non-cacheable

This patch adds an additional flag `XLAT_TABLE_NC` which marks the
translation tables as Non-cacheable for MMU accesses.

Change-Id: I7c28ab87f0ce6

Add support to change xlat_tables to non-cacheable

This patch adds an additional flag `XLAT_TABLE_NC` which marks the
translation tables as Non-cacheable for MMU accesses.

Change-Id: I7c28ab87f0ce67da237fadc3627beb6792860fd4
Signed-off-by: Summer Qin <summer.qin@arm.com>

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Tegra186: reset CPU power state info while onlining

This patch resets the CPU power state info when we online any CPU. The
NS world software would re-init the CPU power state after the CPU gets
onli

Tegra186: reset CPU power state info while onlining

This patch resets the CPU power state info when we online any CPU. The
NS world software would re-init the CPU power state after the CPU gets
online anyways. This allows us to maintain proper CPU/cluster power
states in the MCE firmware at all times.

Change-Id: Ib24054f53df720a4f88d67b2cb5a2e036e475e14
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: fix recursion in included headers (tegra_def.h/platform_def.h)

This patch fixes the "Recursion in included headers" error flagged by
Coverity.

Fixes coverity errors "31858: Recursion in i

Tegra186: fix recursion in included headers (tegra_def.h/platform_def.h)

This patch fixes the "Recursion in included headers" error flagged by
Coverity.

Fixes coverity errors "31858: Recursion in included headers" and
"31857: Recursion in included headers"

Change-Id: Icf8838434b1808b396e743e47f59adc452546364
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: fix logic to calculate TZRAM_ADDR_HI bits

This patch fixes the logic to calculate the higher bits for TZRAM's base/end
addresses.

Fixes coverity error "31853: Wrong operator used

Tegra: memctrl_v2: fix logic to calculate TZRAM_ADDR_HI bits

This patch fixes the logic to calculate the higher bits for TZRAM's base/end
addresses.

Fixes coverity error "31853: Wrong operator used (CONSTANT_EXPRESSION_RESULT)"

Change-Id: Iff62ef18cba59cd41ad63a5c71664872728356a8
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Include all makefiles before build option checks

At present, the build option checks are done prior to inclusion of
BL makefiles. This meant if the BL makefiles modified any of the options
then thes

Include all makefiles before build option checks

At present, the build option checks are done prior to inclusion of
BL makefiles. This meant if the BL makefiles modified any of the options
then these checks were bypassed. This patch corrects this problem.

Change-Id: I0b591392a74d6d456d2b19bbe292f42b5aeae048
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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Re-factor header files for easier PSCI library integration

This patch re-factors the following headers to make it easier to
integrate the PSCI library with an AArch32 Secure Payload :

* bl_commo

Re-factor header files for easier PSCI library integration

This patch re-factors the following headers to make it easier to
integrate the PSCI library with an AArch32 Secure Payload :

* bl_common.h : The entry point information and the param
header data structures are factored out into separate
headers ep_info.h and param_headers.h
* psci.h : The PSCI library interfaces are factored out
into the new header psci_lib.h
* context_mgmt.h : The header file is modified to not include
arch.h when compiled for AArch32 mode.

No functional changes are introduced by this patch.

Change-Id: I5e21a843c0af2ba8e47dee4e577cf95929be8cd4
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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ARM platforms: Add support for MT bit in MPIDR

This patch modifies some of the functions in ARM platform layer to cater
for the case when multi-threading `MT` is set in MPIDR. A new build flag
`ARM_

ARM platforms: Add support for MT bit in MPIDR

This patch modifies some of the functions in ARM platform layer to cater
for the case when multi-threading `MT` is set in MPIDR. A new build flag
`ARM_PLAT_MT` is added, and when enabled, the functions accessing MPIDR
now assume that the `MT` bit is set for the platform and access the bit
fields accordingly.

Also, a new API plat_arm_get_cpu_pe_count is added when `ARM_PLAT_MT` is
enabled, returning the PE count within the physical cpu corresponding to
`mpidr`.

Change-Id: I04ccf212ac3054a60882761f4087bae299af13cb
Signed-off-by: Summer Qin <summer.qin@arm.com>

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Merge pull request #873 from dp-arm/dp/makefile-reorg

Move plat/common source file definitions to generic Makefiles

Merge pull request #872 from dp-arm/dp/fix-typo

firmware-design: Fix typo in ToC header flags specification

Tegra: memctrl_v2: program Video Memory carveout size in MBs

This patch fixes the programming logic for the Video memory carveout's
size. The Memory Controller expects the size in terms of MBs inste

Tegra: memctrl_v2: program Video Memory carveout size in MBs

This patch fixes the programming logic for the Video memory carveout's
size. The Memory Controller expects the size in terms of MBs instead
of bytes.

Change-Id: Ia8261b737448bae9a435fe21ab336126785d4279
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: no stream ID override for Security Engine

This patch removes stream ID override for the Security Engine
hardware block as its stream ID is programmed by the NS world
driver.

Orig

Tegra: memctrl_v2: no stream ID override for Security Engine

This patch removes stream ID override for the Security Engine
hardware block as its stream ID is programmed by the NS world
driver.

Original change by Mallikarjun Kasoju <mkasoju@nvidia.com>

Change-Id: Ia6523c1a1bb0a82bdeb878feb55670813899bdac
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: reset power state info during CPU_ON

This patch resets the power state info for CPUs when onlining,
as we set deepest power when offlining a core but that may not
be requested by non-secur

Tegra186: reset power state info during CPU_ON

This patch resets the power state info for CPUs when onlining,
as we set deepest power when offlining a core but that may not
be requested by non-secure sw which controls idle states. It
will re-init this info from non-secure software when the core
come online.

Original change by Prashant Gaikwad <pgaikwad@nvidia.com>

Change-Id: Id6c2fa2b821c7705aafbb561a62348c36fd3abd8
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: enable support for simulation environment

The Tegra simulation environment has limited capabilities. This patch
checks the chip's major and minor versions to decide the features to
enable/

Tegra186: enable support for simulation environment

The Tegra simulation environment has limited capabilities. This patch
checks the chip's major and minor versions to decide the features to
enable/disable - MCE firmware version checking is disabled and limited
Memory Controller settings are enabled

Change-Id: I258a807cc3b83cdff14a9975b4ab4f9d1a9d7dcf
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: check MCE firmware version during boot

This patch checks that the system is running with the supported MCE
firmware during boot. In case the firmware version does not match the
interface h

Tegra186: check MCE firmware version during boot

This patch checks that the system is running with the supported MCE
firmware during boot. In case the firmware version does not match the
interface header version, then the system halts.

Change-Id: Ib82013fd1c1668efd6f0e4f36cd3662d339ac076
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: fix programming sequence for SC7/SC8 entry

This patch fixes the programming sequence for 'System Suspend' and
'Quasi power down' state entry. The device needs to update the
required power

Tegra186: fix programming sequence for SC7/SC8 entry

This patch fixes the programming sequence for 'System Suspend' and
'Quasi power down' state entry. The device needs to update the
required power state before querying the MCE firmware to see the
entry to that power state is allowed.

Original change by Allen Yu <alleny@nvidia.com>

Change-Id: I65e03754322188af913fabf41f29d1c3595afd85
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: program default core wake mask during CPU_SUSPEND

This patch programs the default CPU wake mask during CPU_SUSPEND. This
reduces the CPU_SUSPEND latency as the system has to send one less

Tegra186: program default core wake mask during CPU_SUSPEND

This patch programs the default CPU wake mask during CPU_SUSPEND. This
reduces the CPU_SUSPEND latency as the system has to send one less SMC
before issuing the actual suspend request.

Original change by Krishna Sitaraman <ksitaraman@nvidia.com>

Change-Id: I1f9351dde4ab30936070e9f42c2882fa691cbe46
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: clear the system cstate for offline core

This patch clears the system cstate when offlining a CPU core as we
need to update the sytem cstate to SC7 only when we enter system
suspend.

Orig

Tegra186: clear the system cstate for offline core

This patch clears the system cstate when offlining a CPU core as we
need to update the sytem cstate to SC7 only when we enter system
suspend.

Original change by Prashant Gaikwad <pgaikwad@nvidia.com>

Change-Id: I1cff9bbab4db7d390a491c8939aea5db6c6b5c59
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: enable APE overrides for chip verification

This patch enables overrides for APE domains to allow the chip verification
software harness (MODS) to execute its test cases.

Original

Tegra: memctrl_v2: enable APE overrides for chip verification

This patch enables overrides for APE domains to allow the chip verification
software harness (MODS) to execute its test cases.

Original change by Harvey Hsieh <hhsieh@nvidia.com>

Change-Id: I09b22376068c5b65d89c2a53154ccb2c60d955bd
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: mce: enable LATIC for chip verification

This patch adds a new interface to allow for making an ARI call that
will enable LATIC for the chip verification software harness.

LATIC allows som

Tegra186: mce: enable LATIC for chip verification

This patch adds a new interface to allow for making an ARI call that
will enable LATIC for the chip verification software harness.

LATIC allows some MINI ISMs to be read in the CCPLEX. The ISMs are
used for various measurements relevant ot particular locations in
Silicon. They are small counters which can be polled to determine
how fast a particular location in the Silicon is.

Original change by Guy Sotomayor <gsotomayor@nvidia.com>

Change-Id: Ifb49b8863a009d4cdd5d1ba38a23b5374500a4b3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: save/restore BL31 context to/from TZDRAM

This patch adds support to save the BL31 state to the TZDRAM
before entering system suspend. The TZRAM loses state during
system suspend and so we

Tegra186: save/restore BL31 context to/from TZDRAM

This patch adds support to save the BL31 state to the TZDRAM
before entering system suspend. The TZRAM loses state during
system suspend and so we need to copy the entire BL31 code to
TZDRAM before entering the state.

In order to restore the state on exiting system suspend, a new
CPU reset handler is implemented which gets copied to TZDRAM
during boot. TO keep things simple we use this same reset handler
for booting secondary CPUs too.

Change-Id: I770f799c255d22279b5cdb9b4d587d3a4c54fad7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: re-configure MSS' client settings

This patch reprograms MSS to make ROC deal with ordering of
MC traffic after boot and system suspend exit. This is needed
as device boots with MSS having

Tegra186: re-configure MSS' client settings

This patch reprograms MSS to make ROC deal with ordering of
MC traffic after boot and system suspend exit. This is needed
as device boots with MSS having all control but POR wants ROC
to deal with the ordering. Performance is expected to improve
with ROC but since no one has really tested the performance,
keep the option configurable for now by introducing a platform
level makefile variable.

Change-Id: I2e782fea138ccf9d281eb043a6b2c3bb97c839a7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge pull request #865 from vwadekar/tegra186-platform-support-v1

Tegra186 platform support v1

Tegra186: implement support for System Suspend

This patch adds the chip level support for System Suspend entry
and exit. As part of the entry sequence we first query the MCE
firmware to check if it

Tegra186: implement support for System Suspend

This patch adds the chip level support for System Suspend entry
and exit. As part of the entry sequence we first query the MCE
firmware to check if it is safe to enter system suspend. Once
we get a green light, we save hardware block settings and enter
the power state. As expected, all the hardware settings are
restored once we exit the power state.

Change-Id: I6d192d7568d6a555eb10efdfd45f6d79c20f74ea
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: memctrl_v2: restore video memory settings

The memory controller loses its settings when the device enters system
suspend state.

This patch adds a handler to restore the Video Memory setti

Tegra186: memctrl_v2: restore video memory settings

The memory controller loses its settings when the device enters system
suspend state.

This patch adds a handler to restore the Video Memory settings in the
memory controller, which would be called after exiting the system suspend
state.

Change-Id: I1ac12426d7290ac1452983d3c9e05fabbf3327fa
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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