docs: hikey: Fix typo

Signed-off-by: Victor Chong <victor.chong@linaro.org>

cpu log buffer size depends on cache line size

Platform may use specific cache line sizes. Since CACHE_WRITEBACK_GRANULE
defines the platform specific cache line size, it is used to define the
size

cpu log buffer size depends on cache line size

Platform may use specific cache line sizes. Since CACHE_WRITEBACK_GRANULE
defines the platform specific cache line size, it is used to define the
size of the cpu data structure CPU_DATA_SIZE aligned on cache line size.

Introduce assembly macro 'mov_imm' for AArch32 to simplify implementation
of function '_cpu_data_by_index'.

Change-Id: Ic2d49ffe0c3e51649425fd9c8c99559c582ac5a1
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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uniphier: work around Boot ROM bug for USB boot mode of PXs3 SoC

Due to a bug in the Boot ROM, the USB load API turned out not working
as expected. It is unfixable because the Boot ROM is hard-wire

uniphier: work around Boot ROM bug for USB boot mode of PXs3 SoC

Due to a bug in the Boot ROM, the USB load API turned out not working
as expected. It is unfixable because the Boot ROM is hard-wired.

Add work around code in TF to bypass the problematic Boot ROM code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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uniphier: fix code indent for conditional statement

checkpatch.pl from Linux reports tons of coding style errors and
warnings. I am just fixing under plat/socionext/uniphier/.

Signed-off-by: Masah

uniphier: fix code indent for conditional statement

checkpatch.pl from Linux reports tons of coding style errors and
warnings. I am just fixing under plat/socionext/uniphier/.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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Merge pull request #1072 from sandrine-bailleux-arm/sb/tsp-mapping

ARM platforms: Map TSP only when TSPD is included

cert_tool: Support for legacy RSA PKCS#1 v1.5

This patch enables choice of RSA version at run time to be used for
generating signatures by the cert_tool. The RSA PSS as defined in
PKCS#1 v2.1 become

cert_tool: Support for legacy RSA PKCS#1 v1.5

This patch enables choice of RSA version at run time to be used for
generating signatures by the cert_tool. The RSA PSS as defined in
PKCS#1 v2.1 becomes the default version and this patch enables to specify
the RSA PKCS#1 v1.5 algorithm to `cert_create` through the command line
-a option. Also, the build option `KEY_ALG` can be used to pass this
option from the build system. Please note that RSA PSS is mandated
by Trusted Board Boot requirements (TBBR) and legacy RSA support is
being added for compatibility reasons.

Fixes ARM-Software/tf-issues#499
Change-Id: Ifaa3f2f7c9b43f3d7b3effe2cde76bf6745a5d73
Co-Authored-By: Eleanor Bonnici <Eleanor.bonnici@arm.com>
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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Export KEY_ALG as a user build option

The `KEY_ALG` variable is used to select the algorithm for key
generation by `cert_create` tool for signing the certificates. This
variable was previously undoc

Export KEY_ALG as a user build option

The `KEY_ALG` variable is used to select the algorithm for key
generation by `cert_create` tool for signing the certificates. This
variable was previously undocumented and did not have a global default
value. This patch corrects this and also adds changes to derive the
value of `TF_MBEDTLS_KEY_ALG` based on `KEY_ALG` if it not set by the
platform. The corresponding assignment of these variables are also now
removed from the `arm_common.mk` makefile.

Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: I78e2d6f4fc04ed5ad35ce2266118afb63127a5a4

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ARM platforms: Map TSP only when TSPD is included

This patch ensures that the ARM_MAP_TSP_SEC_MEM memory region is mapped
in BL2 only if the TSPD has been included in the build. This saves one
entry

ARM platforms: Map TSP only when TSPD is included

This patch ensures that the ARM_MAP_TSP_SEC_MEM memory region is mapped
in BL2 only if the TSPD has been included in the build. This saves one
entry in the plat_arm_mmap[] array and avoids to map extra memory when
it's not needed.

Change-Id: I6ae60822ff8f0de198145925b0b0d45355179a94
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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Merge pull request #1079 from douglas-raillard-arm/dr/doc_fix_typo

porting-guide.rst: Fix some sections' level

Merge pull request #1077 from soby-mathew/sm/fix_juno_assert_lvl

Juno: Define PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO

porting-guide.rst: Fix some sections' level

Fix the level of the section
"13. Function : plat_setup_psci_ops() [mandatory]",
including all the subsections.

Fix the level of the section
"12.7. p

porting-guide.rst: Fix some sections' level

Fix the level of the section
"13. Function : plat_setup_psci_ops() [mandatory]",
including all the subsections.

Fix the level of the section
"12.7. plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional]"
to lower it like the surrounding functions.

Change-Id: I781823bc96ece669f8fde4bd39c4e333c7bf4d1a
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>

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Add CFI debug info to vector entries

Add Call Frame Information assembler directives to vector entries so
that debuggers display the backtrace of functions that triggered a
synchronous exception. Fo

Add CFI debug info to vector entries

Add Call Frame Information assembler directives to vector entries so
that debuggers display the backtrace of functions that triggered a
synchronous exception. For example, a function triggering a data abort
will be easier to debug if the backtrace can be displayed from a
breakpoint at the beginning of the synchronous exception vector.

DS-5 needs CFI otherwise it will not attempt to display the backtrace.
Other debuggers might have other needs. These debug information are
stored in the ELF file but not in the final binary.

Change-Id: I32dc4e4b7af02546c93c1a45c71a1f6d710d36b1
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>

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Juno: Define PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO

This patch fixes the PLAT_LOG_LEVEL_ASSERT to 40 which corresponds
to LOG_LEVEL_INFO. Having this level of log for assertions means that the
`ass

Juno: Define PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO

This patch fixes the PLAT_LOG_LEVEL_ASSERT to 40 which corresponds
to LOG_LEVEL_INFO. Having this level of log for assertions means that the
`assert()` will not generate the strings implied in the expression taken
as parameter. This allows to save some memory when Juno is built for
LOG_LEVEL = LOG_LEVEL_VERBOSE and DEBUG = 1.

Fixes ARM-software/tf-issues#511

Change-Id: Id84a40f803ab07a5a8f6e587167af96694a07d04
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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asm_macros: set the default assembly code alignment to 4 byte

Assembly routines are usually defined by using "func" and "endfunc":

func foo
...
endfunc foo

Currently, the "func" macr

asm_macros: set the default assembly code alignment to 4 byte

Assembly routines are usually defined by using "func" and "endfunc":

func foo
...
endfunc foo

Currently, the "func" macro does not specify ".align" directive
by default. It causes unaligned instruction under some circumstances.

As far as I tested, this problem happens for GCC 5 or older. It did
not happen for GCC 6 or newer. Taking into account that GCC 4.x / 5.x
is still used, make sure that assembly code is at least 4 byte aligned.

[ How to reproduce the problem ]

For example, use GCC 5.3 downloaded from Linaro:
http://releases.linaro.org/components/toolchain/binaries/5.3-2016.05/
aarch64-linux-gnu/gcc-linaro-5.3.1-2016.05-x86_64_aarch64-linux-gnu.tar.xz

Expand mbedtls-2.4.2 to the current directory.

Try the following:

$ git log --oneline -1
77544ef Merge pull request #1071 from jeenu-arm/syntax-fix
$ aarch64-linux-gnu-gcc --version | head -1
aarch64-linux-gnu-gcc (Linaro GCC 5.3-2016.05) 5.3.1 20160412
$ make CROSS_COMPILE=aarch64-linux-gnu- PLAT=uniphier \
TRUSTED_BOARD_BOOT=1 MBEDTLS_DIR=mbedtls-2.4.2
( snip build log )
$ aarch64-linux-gnu-nm build/uniphier/release/bl1/bl1.elf | grep handler
00000000800088f4 T bl1_fwu_smc_handler
00000000800084c8 T bl1_smc_handler
000000008000a6e0 t _panic_handler
000000008000a8e0 W plat_error_handler
000000008000a8e8 W plat_panic_handler
000000008000a8d8 W plat_reset_handler
000000008000a39f T reset_handler
000000008000a367 t smc_handler
000000008000a2ef t smc_handler64

You will notice "smc_handler64", "reset_handler", etc. are not properly
aligned.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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Merge pull request #1069 from Leo-Yan/hikey_enable_watchdog_reset

Hikey: enable watchdog reset

Merge pull request #1074 from EvanLloyd/ejll/62_file_mode

fiptool: Update file open modes with 'b' (for Windows)

Merge pull request #1075 from robertovargas-arm/fix_el3_payload

Don't use zero_normalmem in bl2_platform_setup

Don't use zero_normalmem in bl2_platform_setup

zero_normalmem only can zero memory when caches are enabled
and the target memory is a normal memory, otherwise an abort is
generated. In the case of E

Don't use zero_normalmem in bl2_platform_setup

zero_normalmem only can zero memory when caches are enabled
and the target memory is a normal memory, otherwise an abort is
generated. In the case of EL3_PAYLOAD_BASE bl2_platform_setup was
calling zero_normalmem with device memory and it generated an abort.

Change-Id: If013603f209a12af488a9c54481f97a8f395b26a
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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fiptool: Update file open modes with 'b' (for Windows)

Unix does not distinguish binary and text modes.
On Windows the 'b' flag (e.g. "rb" instead of "r") is used to
indicate that files should be op

fiptool: Update file open modes with 'b' (for Windows)

Unix does not distinguish binary and text modes.
On Windows the 'b' flag (e.g. "rb" instead of "r") is used to
indicate that files should be opened in binary mode.
This has no impact on Unix, but is needed on Windows to avoid
end-of-line issues.

Change-Id: I69424c55735d5d563d36c50bedd6357b8e05137e
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>

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Merge pull request #1073 from davidcunado-arm/dc/update_docs

Add usage note for FVP model versions 11.0 and 8.5

Merge pull request #1066 from islmit01/im/enable_cnp_bit

Enable CnP bit for ARMv8.2 CPUs

Merge pull request #1062 from jeenu-arm/cpu-fixes

Cpu macro fixes

Add usage note for FVP model versions 11.0 and 8.5

The internal synchronisation timings of the FVP model version
11.0 build 11.0.34 and version 8.5 build 0.8.5202 has been
changed compared to older

Add usage note for FVP model versions 11.0 and 8.5

The internal synchronisation timings of the FVP model version
11.0 build 11.0.34 and version 8.5 build 0.8.5202 has been
changed compared to older version of the models.

This change may have an impact on how the model behaves depending
on the workload being run on the model. For example test failures
have been seen where the primary core has powered on a secondary
core but was then starved of host CPU time and so was not able to
update power status, resulting a test failure due to an incorrect
status. This, or similar behaviour, is not to be expected from
real hardware platforms.

This patch adds a usage note on how to launch these models so
that internal synchronisation timing matches that of the older
version of the models, specifically adding the -Q 100 option.

Change-Id: If922afddba1581b7246ec889b3f1598533ea1b7e
Signed-off-by: David Cunado <david.cunado@arm.com>

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Merge pull request #1071 from jeenu-arm/syntax-fix

plat/arm: Fix ARM_INSTANTIATE_LOCK syntax anomaly

Tegra: Rename CORTEX_A57_ACTLR_EL1 to *CPUACTLR*

CORTEX_A57_ACTLR_EL1 macro refers to the CPUACTLR_EL1 register. Since
ACTLR_EL1 is a different register (not implemented in Cortex-A57) this
patch re

Tegra: Rename CORTEX_A57_ACTLR_EL1 to *CPUACTLR*

CORTEX_A57_ACTLR_EL1 macro refers to the CPUACTLR_EL1 register. Since
ACTLR_EL1 is a different register (not implemented in Cortex-A57) this
patch renames this macro for clarity.

Change-Id: I94d7d564cd2423ae032bbdd59a99d2dc535cdff6
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>

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