History log of /rk3399_ARM-atf/ (Results 15026 – 15050 of 18314)
Revision Date Author Comments
(<<< Hide modified files)
(Show modified files >>>)
885ca54a09-May-2018 Dimitris Papastamos <dimitris.papastamos@arm.com>

Merge pull request #1377 from robertovargas-arm/compiler-warnings

Compiler warnings

d92a286309-May-2018 Roberto Vargas <roberto.vargas@arm.com>

xlat: Fix warning in CHECK_VIRT_ADDR_SPACE_SIZE

When TF is compiled for aarch32 MAX_VIRT_ADDR_SPACE_SIZE is 2^32 in some cases,
which makes the test (size) <= MAX_VIRT_ADDR_SPACE_SIZE a tautology be

xlat: Fix warning in CHECK_VIRT_ADDR_SPACE_SIZE

When TF is compiled for aarch32 MAX_VIRT_ADDR_SPACE_SIZE is 2^32 in some cases,
which makes the test (size) <= MAX_VIRT_ADDR_SPACE_SIZE a tautology because
uintptr_t is a 32 bit value. The cast remove the warning for clang.

Change-Id: I1345f3400f8fbbe4ffd3caa990a90e7ba593dba5
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

show more ...

a83a74d209-May-2018 Roberto Vargas <roberto.vargas@arm.com>

Don't use variables as tf_printf format strings

Using variables as format strings can generate security problems when
the user can control those strings. Some compilers generate warnings
in that cas

Don't use variables as tf_printf format strings

Using variables as format strings can generate security problems when
the user can control those strings. Some compilers generate warnings
in that cases, even when the variables are constants and are not
controlled by the user.

Change-Id: I65dee1d1b66feab38cbf298290a86fa56e6cca40
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

show more ...

22fa3a2708-May-2018 danh-arm <dan.handley@arm.com>

Merge pull request #1368 from EvanLloyd/editorconfig

Add .editorconfig file

43d7145208-May-2018 danh-arm <dan.handley@arm.com>

Merge pull request #1354 from robertovargas-arm/mem_protect

ARM platforms: Demonstrate mem_protect from el3_runtime

0b9ce90606-Feb-2018 Jeenu Viswambharan <jeenu.viswambharan@arm.com>

ARM Platforms: Support RAS

- Assign 0x10 for RAS exceptions on ARM platforms, and install
EHF priority descriptor.

- Call the common RAS initialisation from ARM BL31 setup.

- Add empty d

ARM Platforms: Support RAS

- Assign 0x10 for RAS exceptions on ARM platforms, and install
EHF priority descriptor.

- Call the common RAS initialisation from ARM BL31 setup.

- Add empty definitions for platform error records and RAS interrupts.

Change-Id: I0675f299b7840be4c83a9c7a81073a95c605dc90
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

show more ...

1a7c1cfe08-Dec-2017 Jeenu Viswambharan <jeenu.viswambharan@arm.com>

RAS: Add fault injection support

The ARMv8.4 RAS extensions introduce architectural support for software
to inject faults into the system in order to test fault-handling
software. This patch introdu

RAS: Add fault injection support

The ARMv8.4 RAS extensions introduce architectural support for software
to inject faults into the system in order to test fault-handling
software. This patch introduces the build option FAULT_HANDLING_SUPPORT
to allow for lower ELs to use registers in the Standard Error Record to
inject fault. The build option RAS_EXTENSIONS must also be enabled along
with fault injection.

This feature is intended for testing purposes only, and is advisable to
keep disabled for production images.

Change-Id: I6f7a4454b15aec098f9505a10eb188c2f928f7ea
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

show more ...

ca6d918512-Dec-2017 Jeenu Viswambharan <jeenu.viswambharan@arm.com>

RAS: Allow individual interrupt registration

EHF currently allows for registering interrupt handlers for a defined
priority ranges. This is primarily targeted at various EL3 dispatchers
to own range

RAS: Allow individual interrupt registration

EHF currently allows for registering interrupt handlers for a defined
priority ranges. This is primarily targeted at various EL3 dispatchers
to own ranges of secure interrupt priorities in order to delegate
execution to lower ELs.

The RAS support added by earlier patches necessitates registering
handlers based on interrupt number so that error handling agents shall
receive and handle specific Error Recovery or Fault Handling interrupts
at EL3.

This patch introduces a macro, RAS_INTERRUPTS() to declare an array of
interrupt numbers and handlers. Error handling agents can use this macro
to register handlers for individual RAS interrupts. The array is
expected to be sorted in the increasing order of interrupt numbers.

As part of RAS initialisation, the list of all RAS interrupts are sorted
based on their ID so that, given an interrupt, its handler can be looked
up with a simple binary search.

For an error handling agent that wants to handle a RAS interrupt,
platform must:

- Define PLAT_RAS_PRI to be the priority of all RAS exceptions.

- Enumerate interrupts to have the GIC driver program individual EL3
interrupts to the required priority range. This is required by EHF
even before this patch.

Documentation to follow.

Change-Id: I9471e4887ff541f8a7a63309e9cd8f771f76aeda
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

show more ...

362599ec08-Dec-2017 Jeenu Viswambharan <jeenu.viswambharan@arm.com>

RAS: Add support for node registration

Previous patches added frameworks for handling RAS errors. This patch
introduces features that the platform can use to enumerate and iterate
RAS nodes:

- Th

RAS: Add support for node registration

Previous patches added frameworks for handling RAS errors. This patch
introduces features that the platform can use to enumerate and iterate
RAS nodes:

- The REGISTER_RAS_NODES() can be used to expose an array of
ras_node_info_t structures. Each ras_node_info_t describes a RAS
node, along with handlers for probing the node for error, and if
did record an error, another handler to handle it.

- The macro for_each_ras_node() can be used to iterate over the
registered RAS nodes, probe for, and handle any errors.

The common platform EA handler has been amended using error handling
primitives introduced by both this and previous patches.

Change-Id: I2e13f65a88357bc48cd97d608db6c541fad73853
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

show more ...

30d81c3607-Dec-2017 Jeenu Viswambharan <jeenu.viswambharan@arm.com>

RAS: Add helpers to access Standard Error Records

The ARMv8 RAS Extensions introduced Standard Error Records which are a
set of standard registers through which:

- Platform can configure RAS node

RAS: Add helpers to access Standard Error Records

The ARMv8 RAS Extensions introduced Standard Error Records which are a
set of standard registers through which:

- Platform can configure RAS node policy; e.g., notification
mechanism;

- RAS nodes can record and expose error information for error handling
agents.

Standard Error Records can either be accessed via. memory-mapped
or System registers. This patch adds helper functions to access
registers and fields within an error record.

Change-Id: I6594ba799f4a1789d7b1e45b3e17fd40e7e0ba5c
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

show more ...

14c6016a04-Apr-2018 Jeenu Viswambharan <jeenu.viswambharan@arm.com>

AArch64: Introduce RAS handling

RAS extensions are mandatory for ARMv8.2 CPUs, but are also optional
extensions to base ARMv8.0 architecture.

This patch adds build system support to enable RAS feat

AArch64: Introduce RAS handling

RAS extensions are mandatory for ARMv8.2 CPUs, but are also optional
extensions to base ARMv8.0 architecture.

This patch adds build system support to enable RAS features in ARM
Trusted Firmware. A boolean build option RAS_EXTENSION is introduced for
this.

With RAS_EXTENSION, an Exception Synchronization Barrier (ESB) is
inserted at all EL3 vector entry and exit. ESBs will synchronize pending
external aborts before entering EL3, and therefore will contain and
attribute errors to lower EL execution. Any errors thus synchronized are
detected via. DISR_EL1 register.

When RAS_EXTENSION is set to 1, HANDLE_EL3_EA_FIRST must also be set to 1.

Change-Id: I38a19d84014d4d8af688bd81d61ba582c039383a
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

show more ...

76454abf30-Nov-2017 Jeenu Viswambharan <jeenu.viswambharan@arm.com>

AArch64: Introduce External Abort handling

At present, any External Abort routed to EL3 is reported as an unhandled
exception and cause a panic. This patch enables ARM Trusted Firmware to
handle Ext

AArch64: Introduce External Abort handling

At present, any External Abort routed to EL3 is reported as an unhandled
exception and cause a panic. This patch enables ARM Trusted Firmware to
handle External Aborts routed to EL3.

With this patch, when an External Abort is received at EL3, its handling
is delegated to plat_ea_handler() function. Platforms can provide their
own implementation of this function. This patch adds a weak definition
of the said function that prints out a message and just panics.

In order to support handling External Aborts at EL3, the build option
HANDLE_EA_EL3_FIRST must be set to 1.

Before this patch, HANDLE_EA_EL3_FIRST wasn't passed down to
compilation; this patch fixes that too.

Change-Id: I4d07b7e65eb191ff72d63b909ae9512478cd01a1
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

show more ...

ef653d9329-Nov-2017 Jeenu Viswambharan <jeenu.viswambharan@arm.com>

AArch64: Refactor GP register restore to separate function

At present, the function that restores general purpose registers also
does ERET. Refactor the restore code to restore general purpose
regis

AArch64: Refactor GP register restore to separate function

At present, the function that restores general purpose registers also
does ERET. Refactor the restore code to restore general purpose
registers without ERET to complement the save function.

The macro save_x18_to_x29_sp_el0 was used only once, and is therefore
removed, and its contents expanded inline for readability.

No functional changes, but with this patch:

- The SMC return path will incur an branch-return and an additional
register load.

- The unknown SMC path restores registers x0 to x3.

Change-Id: I7a1a63e17f34f9cde810685d70a0ad13ca3b7c50
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

show more ...

0d2a1e4203-May-2018 danh-arm <dan.handley@arm.com>

Merge pull request #1374 from jonathanwright-ARM/jw/fix-memory-leaks-in-fiptool

Fix memory leaks in fiptool

0ef858bd03-May-2018 danh-arm <dan.handley@arm.com>

Merge pull request #1370 from antonio-nino-diaz-arm/an/fix-parange

xlat: Have all values of PARange for 8.x architectures

df7f203303-May-2018 danh-arm <dan.handley@arm.com>

Merge pull request #1367 from robertovargas-arm/ndebug

Remove the unused macro NDEBUG

b14c355e03-May-2018 danh-arm <dan.handley@arm.com>

Merge pull request #1366 from antonio-nino-diaz-arm/an/ignore-spdx

checkpatch: Ignore SPDX_LICENSE_TAG

d1849b9003-May-2018 danh-arm <dan.handley@arm.com>

Merge pull request #1365 from jonathanwright-ARM/jw/fix-cert-create-makefile

Fix the makefile to remove the cert_create executable on 'make realclean'

bf0c112903-May-2018 danh-arm <dan.handley@arm.com>

Merge pull request #1364 from Yann-lms/bl2_at_el3_mmu

BL2_AT_EL3: do not try to disable MMU twice on AARCH32

e9eb146003-May-2018 danh-arm <dan.handley@arm.com>

Merge pull request #1371 from antonio-nino-diaz-arm/an/fix-checkpatch

smccc: Fix checkpatch error in header file

8d28323103-May-2018 Jonathan Wright <jonathan.wright@arm.com>

tools/fiptool: fix memory leaks in fiptool

Free desc->image->buffer before freeing desc->image. We make sure that
the desc->image is non-null before attempting this.

Change-Id: I35c5674629a41d7cf1a

tools/fiptool: fix memory leaks in fiptool

Free desc->image->buffer before freeing desc->image. We make sure that
the desc->image is non-null before attempting this.

Change-Id: I35c5674629a41d7cf1a78b7b41ca4b930d0fb688
Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>

show more ...

d3c4487c02-May-2018 Antonio Nino Diaz <antonio.ninodiaz@arm.com>

xlat: Have all values of PARange for 8.x architectures

In AArch64, the field ID_AA64MMFR0_EL1.PARange has a different set of
allowed values depending on the architecture version.

Previously, we onl

xlat: Have all values of PARange for 8.x architectures

In AArch64, the field ID_AA64MMFR0_EL1.PARange has a different set of
allowed values depending on the architecture version.

Previously, we only compiled the Trusted Firmware with the values that
were allowed by the architecture. However, given that this field is
read-only, it is easier to compile the code with all values regardless
of the target architecture.

Change-Id: I57597ed103dd0189b1fb738a9ec5497391c10dd1
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

show more ...

0c487ea402-May-2018 Antonio Nino Diaz <antonio.ninodiaz@arm.com>

smccc: Fix checkpatch error in header file

Change-Id: Ice141dcc17f504025f922acace94d98f84acba9e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

5d9cef9406-Dec-2017 Evan Lloyd <evan.lloyd@arm.com>

Add .editorconfig file

The .editorconfig file provides an editor agnostic definition of a
project's file format requirements.
Details can be found at http://editorconfig.org/

This change should hav

Add .editorconfig file

The .editorconfig file provides an editor agnostic definition of a
project's file format requirements.
Details can be found at http://editorconfig.org/

This change should have little impact on users, but, it is hoped, will
help those who move across projects avoid making mistakes because of
foreign project editor configuration settings.

Change-Id: I8776526b5ab96b543d3d3e445c60e06b62049e68
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>

show more ...

64af39d001-May-2018 danh-arm <dan.handley@arm.com>

Merge pull request #1362 from robertovargas-arm/dtc-warnings

Remove dtc warnings

1...<<601602603604605606607608609610>>...733