Merge pull request #1433 from sivadur/integration

xilinx: fix zynqmp build when tsp is enabled

xlat_v2: Fix descriptor debug print

The XN, PXN and UXN bits are part of the upper attributes, not the
lower attributes.

Change-Id: Ia5e83f06f2a8de88b551f55f1d36d694918ccbc0
Signed-off-by: Antonio

xlat_v2: Fix descriptor debug print

The XN, PXN and UXN bits are part of the upper attributes, not the
lower attributes.

Change-Id: Ia5e83f06f2a8de88b551f55f1d36d694918ccbc0
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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synquacer: Add platform makefile and documentation

Add Makefile and plaform definations file.
My thanks to Daniel Thompson and Ard Biesheuvel for the bits and pieces
I've taken from their earlier wo

synquacer: Add platform makefile and documentation

Add Makefile and plaform definations file.
My thanks to Daniel Thompson and Ard Biesheuvel for the bits and pieces
I've taken from their earlier work regarding build and deploy steps for
Developerbox based on Synquacer SoCs. They deserve much of the credit
for this work although, since I assembled and tested things, any blame
is probably mine.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Tested-by: Daniel Thompson <daniel.thompson@linaro.org>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

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synquacer: Enable PSCI framework

PSCI framework uses SCPI driver to communicate to SCP firmware for
various power management operations. Following PSCI operations are
supported:
- CPU ON
- CPU OFF
-

synquacer: Enable PSCI framework

PSCI framework uses SCPI driver to communicate to SCP firmware for
various power management operations. Following PSCI operations are
supported:
- CPU ON
- CPU OFF
- CPU STANDBY
- SYSTEM RESET
- SYSTEM OFF

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

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synquacer: Retrieve DRAM info from SCP firmware

Retrieve DRAM info from SCP firmware using SCPI driver. Board supports
multiple DRAM slots so its required to fetch DRAM info from SCP firmware
and pa

synquacer: Retrieve DRAM info from SCP firmware

Retrieve DRAM info from SCP firmware using SCPI driver. Board supports
multiple DRAM slots so its required to fetch DRAM info from SCP firmware
and pass this info to UEFI via non-secure SRAM.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

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synquacer: Add SCPI driver

Add System Control and Power Interface (SCPI) driver which provides APIs
for PSCI framework to work. SCPI driver uses MHU driver APIs to communicate
with SCP firmware for

synquacer: Add SCPI driver

Add System Control and Power Interface (SCPI) driver which provides APIs
for PSCI framework to work. SCPI driver uses MHU driver APIs to communicate
with SCP firmware for various system control and power operations.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

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synquacer: Add MHU driver

Add Message Handling Unit (MHU) driver used to communicate among
Application Processors (AP) and System Control Processor (SCP).

Signed-off-by: Sumit Garg <sumit.garg@lina

synquacer: Add MHU driver

Add Message Handling Unit (MHU) driver used to communicate among
Application Processors (AP) and System Control Processor (SCP).

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

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synquacer: Enable MMU using xlat_tables_v2 library

BL31 runs from SRAM which is a non-coherent memory on synquacer. So
enable MMU with SRAM memory marked as Non-Cacheable and mark page tables
kept o

synquacer: Enable MMU using xlat_tables_v2 library

BL31 runs from SRAM which is a non-coherent memory on synquacer. So
enable MMU with SRAM memory marked as Non-Cacheable and mark page tables
kept on SRAM as Non-Cacheable via XLAT_TABLE_NC flag. Also add page tables
for Device address space.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

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synquacer: Enable System level Generic timer

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

synquacer: Enable GICv3 support

synquacer uses GICv3 compliant GIC500. So enable proper GICv3 driver
initialization.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

synquacer: Enable CCN driver support

synquacer has CCN-512 interconnect. So enable proper CCN driver
initialization.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

synquacer: Implement topology functions

These functions describe the layout of the cores and clusters in order
to support the PSCI framework.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

synquacer: Populate BL32 and BL33 entrypoints

As this platform supports direct entry to BL31 and no BL2, so
populate BL32 and BL33 entrypoints with static memory load info.

Signed-off-by: Sumit Gar

synquacer: Populate BL32 and BL33 entrypoints

As this platform supports direct entry to BL31 and no BL2, so
populate BL32 and BL33 entrypoints with static memory load info.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

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synquacer: Enable PL011 UART Console

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

synquacer: Add platform core management helpers

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

synquacer: Introduce basic platform support

synquacer supports direct entry to BL31 without BL1 and BL2 as
SCP firmware does similar work. So this patch adds BL31 stub APIs.

Signed-off-by: Sumit Ga

synquacer: Introduce basic platform support

synquacer supports direct entry to BL31 without BL1 and BL2 as
SCP firmware does similar work. So this patch adds BL31 stub APIs.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

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plat: xilinx: zynqmp: Get chipid from registers for BL32

This patch reads the chipid registers directly instead of making
pm call when running at BL32. User should ensure that these registers
should

plat: xilinx: zynqmp: Get chipid from registers for BL32

This patch reads the chipid registers directly instead of making
pm call when running at BL32. User should ensure that these registers
should always be accessed from APU in their system configuration.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

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plat: xilinx: zynqmp: Build for DDR if SPD is enabled

This patch builds ATF to DDR if SPD is enabled as it cant fit in
On chip memory(OCM) with SPD enabled. This solves the issue
of build failure wi

plat: xilinx: zynqmp: Build for DDR if SPD is enabled

This patch builds ATF to DDR if SPD is enabled as it cant fit in
On chip memory(OCM) with SPD enabled. This solves the issue
of build failure with SPD enabled for ZynqMP platform.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

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Merge pull request #1403 from glneo/for-upstream-k3

TI K3 platform support

Merge pull request #1421 from Yann-lms/cpp_dtc

Build: add cpp build processing for dtb

Merge pull request #1413 from grandpaul/paulliu-rpi3-0

rpi3: BL32 optee support

SPM: Allow entering the SP without needing a SMC

It may be needed to enter the Secure Partition through other means than
an MM_COMMUNICATE SMC. This patch enables this behaviour by extracting
the ne

SPM: Allow entering the SP without needing a SMC

It may be needed to enter the Secure Partition through other means than
an MM_COMMUNICATE SMC. This patch enables this behaviour by extracting
the necessary code from mm_communicate() and allowing other parts of the
code to use it.

Change-Id: I59f6638d22d9c9d0baff0984f39d056298a8dc8e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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ARM Platforms: Update CNTFRQ register in CNTCTLBase frame

Currently TF-A doesn't initialise CNTFRQ register in CNTCTLBase
frame of the system timer. ARM ARM states that "The instance of
the register

ARM Platforms: Update CNTFRQ register in CNTCTLBase frame

Currently TF-A doesn't initialise CNTFRQ register in CNTCTLBase
frame of the system timer. ARM ARM states that "The instance of
the register in the CNTCTLBase frame must be programmed with this
value as part of system initialization."

The psci_arch_setup() updates the CNTFRQ system register but
according to the ARM ARM, this instance of the register is
independent of the memory mapped instance. This is only an issue
for Normal world software which relies on the memory mapped
instance rather than the system register one.

This patch resolves the issue for ARM platforms.

The patch also solves a related issue on Juno, wherein
CNTBaseN.CNTFRQ can be written and does not reflect the value of
the register in CNTCTLBase frame. Hence this patch additionally
updates CNTFRQ register in the Non Secure frame of the CNTBaseN.

Fixes ARM-Software/tf-issues#593

Change-Id: I09cebb6633688b34d5b1bc349fbde4751025b350
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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Merge pull request #1423 from chandnich/sgi-575/dyncfg

Sgi 575/dyncfg

ti: k3: Introduce basic generic board support

While it would be useful to have a device tree based build, the
required components are not in place yet, so support just a simple
statically defined co

ti: k3: Introduce basic generic board support

While it would be useful to have a device tree based build, the
required components are not in place yet, so support just a simple
statically defined configuration to begin with.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>

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