1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <cassert.h> 11 #include <platform_def.h> 12 #include <stdbool.h> 13 #include <utils_def.h> 14 #include <xlat_tables_v2.h> 15 #include "../xlat_tables_private.h" 16 17 #if (ARM_ARCH_MAJOR == 7) && !defined(ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING) 18 #error ARMv7 target does not support LPAE MMU descriptors 19 #endif 20 21 /* 22 * Returns true if the provided granule size is supported, false otherwise. 23 */ 24 bool xlat_arch_is_granule_size_supported(size_t size) 25 { 26 /* 27 * The library uses the long descriptor translation table format, which 28 * supports 4 KiB pages only. 29 */ 30 return size == PAGE_SIZE_4KB; 31 } 32 33 size_t xlat_arch_get_max_supported_granule_size(void) 34 { 35 return PAGE_SIZE_4KB; 36 } 37 38 #if ENABLE_ASSERTIONS 39 unsigned long long xlat_arch_get_max_supported_pa(void) 40 { 41 /* Physical address space size for long descriptor format. */ 42 return (1ULL << 40) - 1ULL; 43 } 44 #endif /* ENABLE_ASSERTIONS*/ 45 46 bool is_mmu_enabled_ctx(const xlat_ctx_t *ctx __unused) 47 { 48 return (read_sctlr() & SCTLR_M_BIT) != 0; 49 } 50 51 bool is_dcache_enabled(void) 52 { 53 return (read_sctlr() & SCTLR_C_BIT) != 0; 54 } 55 56 uint64_t xlat_arch_regime_get_xn_desc(int xlat_regime __unused) 57 { 58 return UPPER_ATTRS(XN); 59 } 60 61 void xlat_arch_tlbi_va(uintptr_t va, int xlat_regime __unused) 62 { 63 /* 64 * Ensure the translation table write has drained into memory before 65 * invalidating the TLB entry. 66 */ 67 dsbishst(); 68 69 tlbimvaais(TLBI_ADDR(va)); 70 } 71 72 void xlat_arch_tlbi_va_sync(void) 73 { 74 /* Invalidate all entries from branch predictors. */ 75 bpiallis(); 76 77 /* 78 * A TLB maintenance instruction can complete at any time after 79 * it is issued, but is only guaranteed to be complete after the 80 * execution of DSB by the PE that executed the TLB maintenance 81 * instruction. After the TLB invalidate instruction is 82 * complete, no new memory accesses using the invalidated TLB 83 * entries will be observed by any observer of the system 84 * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph 85 * "Ordering and completion of TLB maintenance instructions". 86 */ 87 dsbish(); 88 89 /* 90 * The effects of a completed TLB maintenance instruction are 91 * only guaranteed to be visible on the PE that executed the 92 * instruction after the execution of an ISB instruction by the 93 * PE that executed the TLB maintenance instruction. 94 */ 95 isb(); 96 } 97 98 unsigned int xlat_arch_current_el(void) 99 { 100 /* 101 * If EL3 is in AArch32 mode, all secure PL1 modes (Monitor, System, 102 * SVC, Abort, UND, IRQ and FIQ modes) execute at EL3. 103 * 104 * The PL1&0 translation regime in AArch32 behaves like the EL1&0 regime 105 * in AArch64 except for the XN bits, but we set and unset them at the 106 * same time, so there's no difference in practice. 107 */ 108 return 1U; 109 } 110 111 /******************************************************************************* 112 * Function for enabling the MMU in Secure PL1, assuming that the page tables 113 * have already been created. 114 ******************************************************************************/ 115 void setup_mmu_cfg(uint64_t *params, unsigned int flags, 116 const uint64_t *base_table, unsigned long long max_pa, 117 uintptr_t max_va, __unused int xlat_regime) 118 { 119 uint64_t mair, ttbr0; 120 uint32_t ttbcr; 121 122 assert(IS_IN_SECURE()); 123 124 /* Set attributes in the right indices of the MAIR */ 125 mair = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); 126 mair |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, 127 ATTR_IWBWA_OWBWA_NTR_INDEX); 128 mair |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE, 129 ATTR_NON_CACHEABLE_INDEX); 130 131 /* 132 * Configure the control register for stage 1 of the PL1&0 translation 133 * regime. 134 */ 135 136 /* Use the Long-descriptor translation table format. */ 137 ttbcr = TTBCR_EAE_BIT; 138 139 /* 140 * Disable translation table walk for addresses that are translated 141 * using TTBR1. Therefore, only TTBR0 is used. 142 */ 143 ttbcr |= TTBCR_EPD1_BIT; 144 145 /* 146 * Limit the input address ranges and memory region sizes translated 147 * using TTBR0 to the given virtual address space size, if smaller than 148 * 32 bits. 149 */ 150 if (max_va != UINT32_MAX) { 151 uintptr_t virtual_addr_space_size = max_va + 1U; 152 153 assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size)); 154 /* 155 * __builtin_ctzll(0) is undefined but here we are guaranteed 156 * that virtual_addr_space_size is in the range [1, UINT32_MAX]. 157 */ 158 int t0sz = 32 - __builtin_ctzll(virtual_addr_space_size); 159 160 ttbcr |= (uint32_t) t0sz; 161 } 162 163 /* 164 * Set the cacheability and shareability attributes for memory 165 * associated with translation table walks using TTBR0. 166 */ 167 if ((flags & XLAT_TABLE_NC) != 0U) { 168 /* Inner & outer non-cacheable non-shareable. */ 169 ttbcr |= TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC | 170 TTBCR_RGN0_INNER_NC; 171 } else { 172 /* Inner & outer WBWA & shareable. */ 173 ttbcr |= TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA | 174 TTBCR_RGN0_INNER_WBA; 175 } 176 177 /* Set TTBR0 bits as well */ 178 ttbr0 = (uint64_t)(uintptr_t) base_table; 179 180 #if ARM_ARCH_AT_LEAST(8, 2) 181 /* 182 * Enable CnP bit so as to share page tables with all PEs. This 183 * is mandatory for ARMv8.2 implementations. 184 */ 185 ttbr0 |= TTBR_CNP_BIT; 186 #endif 187 188 /* Now populate MMU configuration */ 189 params[MMU_CFG_MAIR] = mair; 190 params[MMU_CFG_TCR] = (uint64_t) ttbcr; 191 params[MMU_CFG_TTBR0] = ttbr0; 192 } 193