| 485fc954 | 16-May-2018 |
Sughosh Ganu <sughosh.ganu@arm.com> |
RAS: SGI: Add platform handler for RAS interrupts
Add a platform specific handler for RAS interrupts and configure the platform RAS interrupts for EL3 handling. The interrupt handler passes control
RAS: SGI: Add platform handler for RAS interrupts
Add a platform specific handler for RAS interrupts and configure the platform RAS interrupts for EL3 handling. The interrupt handler passes control to StandaloneMM code executing in S-EL0, which populates the CPER buffer with relevant error information. The handler subsequently invokes the SDEI client which processes the information in the error information in the CPER buffer. The helper functions plat_sgi_get_ras_ev_map and plat_sgi_get_ras_ev_map_size would be defined for sgi platforms in the subsequent patch, which adds sgi575 specific RAS changes.
Change-Id: I490f16c15d9917ac40bdc0441659b92380108d63 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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| d9523919 | 16-May-2018 |
Sughosh Ganu <sughosh.ganu@arm.com> |
SPM: SGI: Map memory allocated for secure partitions
The secure partition manager reserves chunks of memory which are used for the S-EL0 StandaloneMM image and the buffers required for communication
SPM: SGI: Map memory allocated for secure partitions
The secure partition manager reserves chunks of memory which are used for the S-EL0 StandaloneMM image and the buffers required for communication between the Non-Secure world with the StandaloneMM image. Add the memory chunks to relevant arrays for mapping the regions of memory with corresponding attributes.
Change-Id: If371d1afee0a50ca7cacd55e16aeaca949d5062b Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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| 2e4a509d | 16-May-2018 |
Sughosh Ganu <sughosh.ganu@arm.com> |
ARM platforms: Allow board specific definition of SP stack base
The SGI platforms need to allocate memory for CPER buffers. These platform buffers would be placed between the shared reserved memory
ARM platforms: Allow board specific definition of SP stack base
The SGI platforms need to allocate memory for CPER buffers. These platform buffers would be placed between the shared reserved memory and the per cpu stack memory, thus the need to redefine stack base pointer for these platforms. This patch allows each board in ARM platform to define the PLAT_SP_IMAGE_STACK_BASE.
Change-Id: Ib5465448b860ab7ab0f645f7cb278a67acce7be9 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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| d9cc9372 | 16-May-2018 |
Sughosh Ganu <sughosh.ganu@arm.com> |
SGI: Include arm_spm_def.h in platform_def.h
Include arm_spm_def.h in the platform_def.h file. Without this inclusion, we get build errors like
In file included from services/std_svc/spm/sp_setup.c
SGI: Include arm_spm_def.h in platform_def.h
Include arm_spm_def.h in the platform_def.h file. Without this inclusion, we get build errors like
In file included from services/std_svc/spm/sp_setup.c:12:0: services/std_svc/spm/sp_setup.c: In function 'spm_sp_setup': services/std_svc/spm/sp_setup.c:61:57: error: 'PLAT_SPM_BUF_BASE' undeclared (first use in this function) write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, PLAT_SPM_BUF_BASE);
Now that the platform_def.h includes arm_spm_def.h, remove inclusion of platform_def.h in arm_spm_def.h to remove the circular dependency.
Change-Id: I5225c8ca33fd8d288849524395e436c3d56daf17 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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| 4576f73c | 12-May-2018 |
Sughosh Ganu <sughosh.ganu@arm.com> |
RAS: ras_common: Add null pointer check for error record probe function
Add a null pointer check for the error record probe function -- avoids a panic in case a platform has not defined it.
Change-
RAS: ras_common: Add null pointer check for error record probe function
Add a null pointer check for the error record probe function -- avoids a panic in case a platform has not defined it.
Change-Id: I1139fa0df33297a12ec16615cacd07540925f991 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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| 46b69e3d | 10-Mar-2018 |
Sughosh Ganu <sughosh.ganu@arm.com> |
Include board_arm_def.h through the platform's header
The board_arm_def.h header file needs to be included via the platform definition header. Not doing so, results in a redefinition error of PLAT_A
Include board_arm_def.h through the platform's header
The board_arm_def.h header file needs to be included via the platform definition header. Not doing so, results in a redefinition error of PLAT_ARM_MAX_BL31_SIZE macro, if defined in the platform definition file.
Change-Id: I1d178f6e8a6a41461e7fbcab9f6813a2faa2d82b Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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| 60e062fb | 25-Jul-2018 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1486 from antonio-nino-diaz-arm/an/psci-misra
Fix several MISRA defects in PSCI library |
| d87d524e | 25-Jul-2018 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1466 from Yann-lms/stm32mp1
Add STMicroelectronics STM32MP1 platform support |
| e16d459d | 25-Jul-2018 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1492 from jts-arm/docs
Reword LOAD_IMAGE_V2 in user guide & fix a typo |
| cad25f14 | 25-Jul-2018 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1491 from jeenu-arm/misra-fix
Arm platforms: Fix type mismatch for arm_pm_idle_states |
| f94523ed | 25-Jul-2018 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1472 from danielboulby-arm/db/Reclaim
Rework page table setup for varying number of mem regions |
| efb3728d | 05-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
Update list of maintainers for STM32MP1
Signed-off-by: Yann Gautier <yann.gautier@st.com> |
| f0958d84 | 16-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: Add platform documentation
Signed-off-by: Yann Gautier <yann.gautier@st.com> |
| f74cbc93 | 16-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: Link BL2, BL32 and DTB in one binary
platform.mk is updated to have compilation rules for DTB, stm32image tool, and the concatenation of the 3 binaries. A new linker script and an assembly
stm32mp1: Link BL2, BL32 and DTB in one binary
platform.mk is updated to have compilation rules for DTB, stm32image tool, and the concatenation of the 3 binaries. A new linker script and an assembly file are added to manage this.
Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Mathieu Belou <mathieu.belou@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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| 5fbcdd05 | 05-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
tools: Add stm32image tool into TF-A
This tools adds a specific header to ST TF-A binary. This header is used by STM32MP1 ROM code to check the bootloader.
Signed-off-by: Yann Gautier <yann.gautier
tools: Add stm32image tool into TF-A
This tools adds a specific header to ST TF-A binary. This header is used by STM32MP1 ROM code to check the bootloader.
Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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| 587f60fa | 05-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: Add device tree files
Those device tree files are taken from STM32MP1 U-Boot and Linux. And they are updated to fit TF-A needs.
Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-of
stm32mp1: Add device tree files
Those device tree files are taken from STM32MP1 U-Boot and Linux. And they are updated to fit TF-A needs.
Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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| 964dfee1 | 16-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: Add BL32 SP_min secure monitor
Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Mathieu Belou <mathieu.belou@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> S
stm32mp1: Add BL32 SP_min secure monitor
Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Mathieu Belou <mathieu.belou@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
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| 10a511ce | 24-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: Add DDR support and its security with TZC400
The DDR driver is under dual license, BSD and GPLv2. The configuration parameters are taken from device tree.
Signed-off-by: Yann Gautier <yan
stm32mp1: Add DDR support and its security with TZC400
The DDR driver is under dual license, BSD and GPLv2. The configuration parameters are taken from device tree.
Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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| e4f559ff | 16-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: Add PMIC support
If a PMIC companion chip is present on board, it has to be configured for regulators supplies. This check is done with board DT configuration.
Signed-off-by: Yann Gautier
stm32mp1: Add PMIC support
If a PMIC companion chip is present on board, it has to be configured for regulators supplies. This check is done with board DT configuration.
Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Pascal Paillet <p.paillet@st.com>
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| 278c34df | 05-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: Add console support
Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> |
| e58a53fb | 20-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: save boot information in backup registers
This will be used by BL33 to get boot device and instance.
Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Mathieu Belou <mathie
stm32mp1: save boot information in backup registers
This will be used by BL33 to get boot device and instance.
Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Mathieu Belou <mathieu.belou@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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| 6a339a49 | 13-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: Add GPIO support
The management of pinctrl nodes of device tree is also added.
Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Mathieu Belou <mathieu.belou@st.com> Signed
stm32mp1: Add GPIO support
The management of pinctrl nodes of device tree is also added.
Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Mathieu Belou <mathieu.belou@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
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| 7839a050 | 24-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: Add clock and reset support
The clock driver is under dual license, BSD and GPLv2. The clock driver uses device tree, so a minimal support for this is added. The required files for driver
stm32mp1: Add clock and reset support
The clock driver is under dual license, BSD and GPLv2. The clock driver uses device tree, so a minimal support for this is added. The required files for driver and DTS files are in include/dt-bindings/.
Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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| 4353bb20 | 16-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
Introduce STMicroelectronics STM32MP1 platform
STM32MP1 is a microprocessor designed by STMicroelectronics, based on a dual Arm Cortex-A7. It is an Armv7-A platform, using dedicated code from TF-A.
Introduce STMicroelectronics STM32MP1 platform
STM32MP1 is a microprocessor designed by STMicroelectronics, based on a dual Arm Cortex-A7. It is an Armv7-A platform, using dedicated code from TF-A.
STM32MP1 uses BL2 compiled with BL2_AT_EL3.
Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Mathieu Belou <mathieu.belou@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Pascal Paillet <p.paillet@st.com>
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| 836be059 | 05-Jul-2018 |
Yann Gautier <yann.gautier@st.com> |
Add STMicroelectronics to the list of contributors
Signed-off-by: Yann Gautier <yann.gautier@st.com> |