imx7: hab_arch: Provide a hab_arch.h file

In order to enable compile time differences in HAB interaction, we should
split out the definition of the base address of the HAB API.

Some version of the

imx7: hab_arch: Provide a hab_arch.h file

In order to enable compile time differences in HAB interaction, we should
split out the definition of the base address of the HAB API.

Some version of the i.MX series have different offsets from the BootROM
base for the HAB callback table.

This patch defines the header into which we will define the i.MX7 specific
offset. The offset of the i.MX7 function-callback table is simultaneously
defined.

Once done, we can latch a set of common function pointer locations from the
offset given here and if necessary change the offset for different
processors without any other code-change.

For now all we support is i.MX7 so the only offset being defined is that
for the i.MX7.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>

show more ...

imx: imx_snvs: Add an SNVS core functionality

This patch adds snvs.c with a imx_snvs_init() function.

imx_snvs_init() sets up permissions of the RTC via the SNVS HPCOMR.

During previous work with

imx: imx_snvs: Add an SNVS core functionality

This patch adds snvs.c with a imx_snvs_init() function.

imx_snvs_init() sets up permissions of the RTC via the SNVS HPCOMR.

During previous work with OPTEE on the i.MX7 part we discovered that prior
to switching from secure-world to normal-world it is required to apply more
permissive permissions than are defaulted to in order for Linux to be able
to access the RTC and CAAM functionality in general.

This patch pertains to fixing the RTC permissions by way of the
HPCOMR.NPSWA_EN bit.

Once set non-privileged code aka Linux-kernel code has permissions to
access the SNVS where the RTC resides.

Perform that permissions fix in imx_snvs_init() now, with a later patch making
the call from our platform setup code.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

show more ...

imx: imx_snvs: Define a SNVS header and memory map

This commit defines two things.

- The basic SNVS memory map. At the moment that is total overkill for the
permission bits we need to set inside

imx: imx_snvs: Define a SNVS header and memory map

This commit defines two things.

- The basic SNVS memory map. At the moment that is total overkill for the
permission bits we need to set inside the SNVS but, for the sake of
completeness define the whole SNVS area as a struct.

- The bits of the HPCOMR register

A permission fix will need to be applied to the SNVS block prior to
switching on TrustZone. All we need to do is waggle a bit in the HPCOMR
register. To do that waggle we first need to define the bits of the
HPCOMR register.

- A imx_snvs_init() function definition

Declare the snvs_init() function so that it can be called from our
platform setup code.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

show more ...

imx: imx_csu: Add a simple CSU layer

- Add a header to define imx_csu_init().
- Defines the Central Security Unit's Config Security Level
permission bits.
- Define CSU_CSL_OPEN_ACCESS permission b

imx: imx_csu: Add a simple CSU layer

- Add a header to define imx_csu_init().
- Defines the Central Security Unit's Config Security Level
permission bits.
- Define CSU_CSL_OPEN_ACCESS permission bitmask
- Run a loop to setup peripheral CSU permissions

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

show more ...

imx: imx_aips: Add initial AIPS support

This patch adds an initial AHB-to-IP TrustZone (AIPS-TZ) initialization
routine. Setting up the AIPSTZ controller is required to inform the SoC
interconnect f

imx: imx_aips: Add initial AIPS support

This patch adds an initial AHB-to-IP TrustZone (AIPS-TZ) initialization
routine. Setting up the AIPSTZ controller is required to inform the SoC
interconnect fabric which bus-masters can read/write and if the read/writes
are buffered.

For our purposes the initial configuration is for everything to be open. We
can lock-down later on as necessary.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

show more ...

imx: imx_io_mux: Define an IO-mux layer

This patch defines:

- The full range of IO-mux register offsets relative to the base address of
the IO-mux block base address.

- The bits for muxing the U

imx: imx_io_mux: Define an IO-mux layer

This patch defines:

- The full range of IO-mux register offsets relative to the base address of
the IO-mux block base address.

- The bits for muxing the UART1 TX/RX lines.

- The bits for muxing the UART6 TX/RX lines.

- The pad control pad bits for the UART

Two functions are provided to configure pad muxes:

- void io_muxc_set_pad_alt_function(pad_mux_offset, alt_function)
Takes a pad_mux_offset and sets the alt_function bit-mask supplied.
This will have the effect of switching the pad into one of its defined
peripheral functions. These peripheral function modes are defined in the
NXP documentation and need to be referred to in order to correctly
configure a new alternative-function.

- void io_muxc_set_pad_features(pad_feature_offset, pad_features)
Takes a pad_feature_offset and applies a pad_features bit-mask to the
indicated pad.
This function allows the setting of PAD drive-strength, pull-up values,
hysteresis glitch filters and slew-rate settings.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

show more ...

imx7: imx7_clock: usb: Initialize the USB core clocks

This patch initializes USB core clocks for the i.MX7.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

imx7: imx7_clock: wdog: Initialize the watchdog clocks

This patch initializes the watchdog clocks for the i.MX7.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

imx7: imx7_clock: uart: Add UART clock init logic

This patch adds an internal UART init routine that gets called from the
external facing clock init function.

In the first pass this call does an ex

imx7: imx7_clock: uart: Add UART clock init logic

This patch adds an internal UART init routine that gets called from the
external facing clock init function.

In the first pass this call does an explicit disable of all UART
clock-gates. Later changes will enable only the UART clock-gates we care
about.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

show more ...

imx: imx_clock: usb: Add USB clock API

This set of patches adds a very minimal layer of USB enabling patches to
clock.c. Unlike the watchdog or UART blocks the USB clocks pertain to PHYs,
the main U

imx: imx_clock: usb: Add USB clock API

This set of patches adds a very minimal layer of USB enabling patches to
clock.c. Unlike the watchdog or UART blocks the USB clocks pertain to PHYs,
the main USB clock etc, not to different instances of the same IP block.

As a result this patch-set takes the clock CCGR clock identifier directly
rather than as an index of an instance of blocks of the same type.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

show more ...

imx: imx_clock: wdog: Add watchdog clock API

This patch adds a set of functions to enable the clock for each of the
watchdog IP blocks.

Unlike the MMC and UART blocks, the watchdog blocks operate o

imx: imx_clock: wdog: Add watchdog clock API

This patch adds a set of functions to enable the clock for each of the
watchdog IP blocks.

Unlike the MMC and UART blocks, the watchdog blocks operate off of the one
root clock, only the clock-gates are enable/disabled individually.

As a consequence the function clock_set_wdog_clk_root_bits() is used to set
the root-slice just once for all of the watchdog blocks.

Future implementations may need to change this model but for now on the one
supported processor and similar NXP SoCs this model should work fine.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

show more ...

imx: imx_clock: mmc: Add USDHC clock API

This patch adds an API to configure up the base USDHC clocks, taking a
bit-mask of silicon specific bits as an input from a higher layer in order
to direct t

imx: imx_clock: mmc: Add USDHC clock API

This patch adds an API to configure up the base USDHC clocks, taking a
bit-mask of silicon specific bits as an input from a higher layer in order
to direct the necessary clock source.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

show more ...

imx: imx_clock: uart: Add UART clock API

This patch adds an API to configure up the base UART clocks, taking a
bit-mask of silicon specific bits as an input from a higher layer in order
to direct th

imx: imx_clock: uart: Add UART clock API

This patch adds an API to configure up the base UART clocks, taking a
bit-mask of silicon specific bits as an input from a higher layer in order
to direct the necessary clock source.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

show more ...

imx: imx_clock: Add driver and associated clock register definitions

This commit:

- Defines a clock stub with a conjoined header defining the clock
memory map.

- Defines the CCM Clock Gating Reg

imx: imx_clock: Add driver and associated clock register definitions

This commit:

- Defines a clock stub with a conjoined header defining the clock
memory map.

- Defines the CCM Clock Gating Register which comes in a quadrumvirate
register set to read, set, clear and toggle individual clock gates into
one of four states based bitmask.

00: Domain clocks not needed
01: Domain clocks needed when in RUN
10: Domain clocks needed when in RUN and WAIT
11: Domain clocks needed all the time

- Defines clock control register bits

There are various quadrumvirate register blocks target-root, misc-root,
post-root, pre-root in the CCM.

The number of registers is huge but the four registers in each
quadrumvirate block contain the same bits, so the number of bit
definitions is actually quite low.

- Defines clock identifiers

An array of clock gates is provided in the CCM block. In order to index
that array and thus enable/disable clock gates for the right components,
we need to provide meaningful names to the indices.

Section 5.2.5 of the i.MX7 Solo Application Processor Reference Manual
Rev 0.1 provides the relevant details.

- Defines target mux select bits
This is a comprehensive definition of the target clock mux select bits.
These bits are required to correctly select the clock source. Defining
all of the bits up-front even for unused blocks in ATF means we can
switch on any block we want at a later date without having to write new
code in the clock-mux layer.

- Defines identifier indices into root-slice array
The root-slice array of control registers has a specific set of indices,
which differ from the clock-gate indices.

- Provides a clock gate enable/disable routine
Provides a clock-gate enable/disable routine via the set/clr
registers in a given clock-gate control register block.

This index passed should be one of the enums associated with CCM and
depending on enable/disable being passed either set or clr will be
written to.

The Domain0 bits are currently the only bits targeted by this write, more
work may need to be done on the domain bits in subsequent patches as a
result.

- imx: Adds set/clr routines to clock layer

Adds a set and clr routine to the clock layer. These routines allow us to
access the set and clear registers of the "target" block registers. These
are the registers where we select the clock source from the available list.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

show more ...

imx7: imx_regs: Add a shared imx-regs.h for i.MX7 ATF platforms

In order to have some common code shared between similar SOCs its pretty
common to have IP blocks reused. In reusing those blocks we f

imx7: imx_regs: Add a shared imx-regs.h for i.MX7 ATF platforms

In order to have some common code shared between similar SOCs its pretty
common to have IP blocks reused. In reusing those blocks we frequently need
to map compatible blocks to different addresses depending on the SOC.

This patch adds a basic memory map of the i.MX7 based on the "Cortex-A7
Memory Map" section 2.12 of "i.MX7Solo Applications Processor Reference
Manual, Rev 0.1 08/2016"

In memory map terms the i.MX7S and i.MX7D are identical with the D
variant containing two Cortex-A7 cores plus a Cortex-M core and the S
variant containing one Cortex-A7 and one Cortex-M.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

show more ...

drivers: imx: mxc_usdhc: Add USDHC driver to support boot EMMC

Add USDHC driver to support boot EMMC. Only initialization
and single/multiple block read are tested.

[bod: fixed checkpatch.pl compla

drivers: imx: mxc_usdhc: Add USDHC driver to support boot EMMC

Add USDHC driver to support boot EMMC. Only initialization
and single/multiple block read are tested.

[bod: fixed checkpatch.pl complaints]
[bod: changed name to imx_usdhc for namespace consistency]
[bod: squashed antecedent fixes into this one patch]

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

show more ...

zynqmp: Add ATF support for Data blob encryption and decryption

This patch adds ATF support for AES data blob encrypt/decrypt.
ATF establishes a path to send the address of the structure
to the xils

zynqmp: Add ATF support for Data blob encryption and decryption

This patch adds ATF support for AES data blob encrypt/decrypt.
ATF establishes a path to send the address of the structure
to the xilsecure, so that it will pick addresses of the data
and performs the requested operation (encrypt/decrypt) and puts
the result in load address.

where structure contains
- Data blob src address
- load address
- IV address
- Key address - this will actual key addr in case of KUP
else it will be zero.
- Data-size
- Aes-op type
- KeySrc

Signed-off-by: Kalyani Akula <kalyani.akula@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

show more ...

zynqmp: Remove emulation platform support

This patch removes support for emulation platforms
EP108 and Veloce.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

zynqmp: pm: Correct function header of clock APIs

Correct function header of pm_api_clock_getparent() and
pm_api_clock_setparent().

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Acked-by: Will

zynqmp: pm: Correct function header of clock APIs

Correct function header of pm_api_clock_getparent() and
pm_api_clock_setparent().

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Acked-by: Will Wong <WILLW@xilinx.com>

show more ...

zynqmp: pm_service: Ignore enable/disable of PLL type clocks

PLL type clock is enabled by FSBL on boot-up. PMUFW enable/disable
them based on their user count. So, it should not be handled from ATF.

zynqmp: pm_service: Ignore enable/disable of PLL type clocks

PLL type clock is enabled by FSBL on boot-up. PMUFW enable/disable
them based on their user count. So, it should not be handled from ATF.

Put PLL type clock into bypass and reset mode only while changing
PLL rate (FBDIV).

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

show more ...

zynqmp: Add new API for pl configuration readback

This patch adds new API's for performing pl configuration
readback.

Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Signe

zynqmp: Add new API for pl configuration readback

This patch adds new API's for performing pl configuration
readback.

Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

show more ...

zynqmp: pm: Use critical flag instead of initenable

CCF has already provision to enable clock during registration
through CLK_IS_CRITICAL flag. Use CLK_IS_CRITICAL instead of
init_enable attribute.

zynqmp: pm: Use critical flag instead of initenable

CCF has already provision to enable clock during registration
through CLK_IS_CRITICAL flag. Use CLK_IS_CRITICAL instead of
init_enable attribute.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Acked-by: Jolly Shah <jolly.shah@xilinx.com>

show more ...

zynqmp: pm: Correct WDT clock database

WDT used by APU is FPD_WDT. FPD WDT clock is controlled by
FPD_SLCR.WDT_CLK_SEL register. Correct the same in WDT clock
database.

As per FPD_SLCR.WDT_CLK_SEL

zynqmp: pm: Correct WDT clock database

WDT used by APU is FPD_WDT. FPD WDT clock is controlled by
FPD_SLCR.WDT_CLK_SEL register. Correct the same in WDT clock
database.

As per FPD_SLCR.WDT_CLK_SEL register, there can be only two
parents of WDT clock not three. Fix the same by correcting it's
parents in clock database.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Acked-by: Jolly Shah <jolly.shah@xilinx.com>

show more ...

zynqmp: pm_service: Add support for writing to AFI registers

Add support for writing to AFI registers.
So that after writing a bitstream the interface can be programmed.

Signed-off-by: Shubhrajyoti

zynqmp: pm_service: Add support for writing to AFI registers

Add support for writing to AFI registers.
So that after writing a bitstream the interface can be programmed.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

show more ...

zynqmp: pm: Add IOCTL to set boot health status

Since the MMIO read/write APIs are removed from Linux user space,
Linux cannot directly write to the Global General Storage Register 4
any more to set

zynqmp: pm: Add IOCTL to set boot health status

Since the MMIO read/write APIs are removed from Linux user space,
Linux cannot directly write to the Global General Storage Register 4
any more to set healthy boot status.

Create an IOCTL to allow Linux to set boot health status.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Acked-by: Will Wong <willw@xilinx.com>

show more ...