1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <mmio.h> 8 #include <platform.h> 9 #include <platform_def.h> 10 #include <sunxi_def.h> 11 #include <xlat_tables_v2.h> 12 13 #include "sunxi_private.h" 14 15 static mmap_region_t sunxi_mmap[PLATFORM_MMAP_REGIONS + 1] = { 16 MAP_REGION_FLAT(SUNXI_SRAM_BASE, SUNXI_SRAM_SIZE, 17 MT_MEMORY | MT_RW | MT_SECURE), 18 MAP_REGION_FLAT(SUNXI_DEV_BASE, SUNXI_DEV_SIZE, 19 MT_DEVICE | MT_RW | MT_SECURE), 20 MAP_REGION(SUNXI_DRAM_BASE, SUNXI_DRAM_VIRT_BASE, SUNXI_DRAM_SEC_SIZE, 21 MT_MEMORY | MT_RW | MT_SECURE), 22 MAP_REGION(PLAT_SUNXI_NS_IMAGE_OFFSET, 23 SUNXI_DRAM_VIRT_BASE + SUNXI_DRAM_SEC_SIZE, 24 SUNXI_DRAM_MAP_SIZE, 25 MT_MEMORY | MT_RO | MT_NS), 26 {}, 27 }; 28 29 unsigned int plat_get_syscnt_freq2(void) 30 { 31 return SUNXI_OSC24M_CLK_IN_HZ; 32 } 33 34 uintptr_t plat_get_ns_image_entrypoint(void) 35 { 36 #ifdef PRELOADED_BL33_BASE 37 return PRELOADED_BL33_BASE; 38 #else 39 return PLAT_SUNXI_NS_IMAGE_OFFSET; 40 #endif 41 } 42 43 void sunxi_configure_mmu_el3(int flags) 44 { 45 mmap_add_region(BL31_BASE, BL31_BASE, 46 BL31_LIMIT - BL31_BASE, 47 MT_MEMORY | MT_RW | MT_SECURE); 48 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 49 BL_CODE_END - BL_CODE_BASE, 50 MT_CODE | MT_SECURE); 51 mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE, 52 BL_RO_DATA_END - BL_RO_DATA_BASE, 53 MT_RO_DATA | MT_SECURE); 54 mmap_add(sunxi_mmap); 55 init_xlat_tables(); 56 57 enable_mmu_el3(0); 58 } 59 60 #define SRAM_VER_REG (SUNXI_SYSCON_BASE + 0x24) 61 uint16_t sunxi_read_soc_id(void) 62 { 63 uint32_t reg = mmio_read_32(SRAM_VER_REG); 64 65 /* Set bit 15 to prepare for the SOCID read. */ 66 mmio_write_32(SRAM_VER_REG, reg | BIT(15)); 67 68 reg = mmio_read_32(SRAM_VER_REG); 69 70 /* deactivate the SOCID access again */ 71 mmio_write_32(SRAM_VER_REG, reg & ~BIT(15)); 72 73 return reg >> 16; 74 } 75