doc: marvell: Update build manual with new memory layouts

Add description for memory layouts used by EspressoBin v7 (DDR4)

Change-Id: I199d8b52580b26e560f14b503a6e99d32de4f284
Signed-off-by: Konsta

doc: marvell: Update build manual with new memory layouts

Add description for memory layouts used by EspressoBin v7 (DDR4)

Change-Id: I199d8b52580b26e560f14b503a6e99d32de4f284
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/61279
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>

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fix: a3900: pm: fix number of CPU power switches.

- Number of open power switches for CPUs should be three
and now two.

- This patch updates the value of open power switches from
0xfd (two powe

fix: a3900: pm: fix number of CPU power switches.

- Number of open power switches for CPUs should be three
and now two.

- This patch updates the value of open power switches from
0xfd (two power-switches) to 0xfc (three power-switches).

Change-Id: I2783ab7f04bbbb6da78eeedcabe4636f9a774512
Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

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svc: Update the EEPROM AVS values processing

Add support for SVC test builds for tuning AVS values.
Update the SVC procedure and add EEPROM access.
Add support for AP807 AVS values (10 bits wide).

svc: Update the EEPROM AVS values processing

Add support for SVC test builds for tuning AVS values.
Update the SVC procedure and add EEPROM access.
Add support for AP807 AVS values (10 bits wide).

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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ble: ap807: Switch to PLL mode and update CPU frequency

- Update CPU frequency on AP807 to 2GHz for SAR 0x0.
- Increase AVS to 0.88V for 2GHz clock

Change-Id: Ic945b682ab2f8543e34294bfc56c3eae2c5e0

ble: ap807: Switch to PLL mode and update CPU frequency

- Update CPU frequency on AP807 to 2GHz for SAR 0x0.
- Increase AVS to 0.88V for 2GHz clock

Change-Id: Ic945b682ab2f8543e34294bfc56c3eae2c5e0c8e
Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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mvebu: cp110: avoid pcie power on/off sequence when called from Linux

In Armada 8K DB boards, PCIe initialization can be executed only once
because PCIe reset performed during chip power on and it c

mvebu: cp110: avoid pcie power on/off sequence when called from Linux

In Armada 8K DB boards, PCIe initialization can be executed only once
because PCIe reset performed during chip power on and it cannot be
executed via GPIO later.
This means that power on can be executed only once, when it's called
from the bootloader.
Power on:
Read bit 21 of the mode, it marks if the caller is
the bootloader or the Linux Kernel.
Power off:
Check if the comphy was already configured to PCIe, if yes,
check if the caller is bootloader, if both conditions are true
(PCIe mode and called by Linux) - skip the power-off.

In addition, fix incorrect documentation describing mode fields -
PCIe width is 3 bits, not 2.

NOTE: with this patch, please use LK4.14.76 (LK4.4.120 may not work
with it).

Change-Id: I4b929011f97a0a1869a51ba378687e78b3eca4ff
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

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plat: marvell: a3700: do not power off cpu due to errata ref #13

Do not power off the CPU1 since there is no way to wake it up
(wake-up is causing CPU0 reset as well duo to HW bug). Quote from errat

plat: marvell: a3700: do not power off cpu due to errata ref #13

Do not power off the CPU1 since there is no way to wake it up
(wake-up is causing CPU0 reset as well duo to HW bug). Quote from errata
Ref #13 [In power saving mode, both cores must be powered off]:
"When Core 0 is on and Core 1 is in power-off state, a Core 1
wake-up resets Core 0 as well and puts Core 0 back to ROM".

To overcome described HW bug instead of powering the CPU off, let it
reach WFI instruction, which is invoked by generic psci_do_cpu_off
function after platform handler finishes. This will put the core in low
power state and give a chance to wake it up.

Before this change, after running secondary kernel via kexec, only one
core was up, now both cores are up.

Change-Id: I87f144867550728055d9b8a2edb84a14539acab7
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

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mvebu: cp110: fix phy selector configuration for XFI1

Extended phy selector configuration about XFI1 mode.

Change-Id: I1309770bbb5fdbfb0127b6f12ee78974d1d6b19f
Signed-off-by: Grzegorz Jaszczyk <jaz

mvebu: cp110: fix phy selector configuration for XFI1

Extended phy selector configuration about XFI1 mode.

Change-Id: I1309770bbb5fdbfb0127b6f12ee78974d1d6b19f
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

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drivers: add tzc380 support

Add tzc380 support.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>

drivers: st: mmc: improve error cases in send_cmd function

Signed-off-by: Yann Gautier <yann.gautier@st.com>

stm32mp: check stm32_sdmmc2_mmc_init return

Signed-off-by: Yann Gautier <yann.gautier@st.com>

drivers: mmc: check mmc_reset_to_idle return

Signed-off-by: Yann Gautier <yann.gautier@st.com>

Merge pull request #1699 from chandnich/sgi-mt-support

Add support to implement multi-threaded platforms for SGI

plat/arm/sgi: Use platform specific functions to get platform ids

Add two new functions 'plat_arm_sgi_get_platform_id' and
'plat_arm_sgi_get_config_id' which will be implemented by all the
SGI platf

plat/arm/sgi: Use platform specific functions to get platform ids

Add two new functions 'plat_arm_sgi_get_platform_id' and
'plat_arm_sgi_get_config_id' which will be implemented by all the
SGI platforms. These functions can be used to determine the part
number and configuration id of the SGI platforms.

In BL2, these functions are used to populate the 'system-id' node.
In BL31, these functions are used to populate the 'sgi_plat_info_t'
structure with the part number and configuration id of the platform.

Change-Id: I3bacda933527724a3b4074ad4ed5b53a81ea4689
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

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Merge pull request #1701 from chandnich/psci-ops

remove weak implemention of 'plat_arm_psci_override_pm_ops'

hikey960: initialize EDMAC and channels

This is needed to utilize the DMA controller on the hikey960

Signed-off-by: Ryan Grachek <ryan@edited.us>

Merge pull request #1688 from JoelHutton/jh/variant_1_mitigations

Initial Spectre V1 mitigations (CVE-2017-5753).

Merge pull request #1698 from hzhuang1/rm_emmc_delay

Rm emmc delay

Merge pull request #1679 from pangupta/master

ccn: Introduce API to set and read value of node register

plat/arm: remove weak implemention of 'plat_arm_psci_override_pm_ops' function

In order to allow Arm platforms to override the default list of PSCI
callbacks, remove the existing weak implementation

plat/arm: remove weak implemention of 'plat_arm_psci_override_pm_ops' function

In order to allow Arm platforms to override the default list of PSCI
callbacks, remove the existing weak implementation of
'plat_arm_psci_override_pm_ops' function and let all the Arm platforms
implement their own 'plat_arm_psci_override_pm_ops' function.

For platforms that support SCMI protocol, the function
'css_scmi_override_pm_ops' can be additionally used as well to
override the default PSCI callbacks.

Change-Id: If7c27468bd51a00ea9c2a3716b5894163f5a9f3c
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

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Merge pull request #1693 from jeenu-arm/ehf-doc

EHF and RAS documentation

Merge pull request #1696 from satheesbalya-arm/sb1/sb1_2406_romlib_juno

romlib: Add juno support for romlib

Merge pull request #1695 from satheesbalya-arm/sb1/sb1_2641_romlib_phase2

romlib: Allow patching of romlib functions

plat/arm/sgi: allow value of PLAT_MAX_PWR_LVL to be platform specific

For platforms with multi-threaded CPUs, the number of power domains
supported would be more than the value currently defined by

plat/arm/sgi: allow value of PLAT_MAX_PWR_LVL to be platform specific

For platforms with multi-threaded CPUs, the number of power domains
supported would be more than the value currently defined by
PLAT_MAX_PWR_LVL. So move the PLAT_MAX_PWR_LVL macro to platform
specific code and let the platform define the number of power domain
levels.

Change-Id: I21c0682e62b397860b2999031a0c9c5ce0d28eed
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

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plat/arm/sgi: override weak implementation of plat_arm_get_cpu_pe_count

To support platforms which are based on multi-threaded CPUs, override
the weak implementation of plat_arm_get_cpu_pe_count fun

plat/arm/sgi: override weak implementation of plat_arm_get_cpu_pe_count

To support platforms which are based on multi-threaded CPUs, override
the weak implementation of plat_arm_get_cpu_pe_count function to return
the number of threads supported by the CPU used in the platform.

Change-Id: Ia680773f1277b17e2d3d2414d87943dcece33e89
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

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plat/arm/common: add an additional platform power level

For platforms using multi-threaded CPUs, there can be upto four
platform power domain levels. At present, there are three platform
power domai

plat/arm/common: add an additional platform power level

For platforms using multi-threaded CPUs, there can be upto four
platform power domain levels. At present, there are three platform
power domain levels that are defined for the CSS platforms. Define a
fourth level 'ARM_PWR_LVL3' as well to provide support for an
additional platform power domain level.

Change-Id: I40cc17a10f4690a560776f504364fd7277a7e72a
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

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