Cleanup context handling library

Minor style cleanup.

Change-Id: Ief19dece41a989e2e8157859a265701549f6c585
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Merge pull request #1834 from thloh85-intel/s10_bl31

plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform

Merge pull request #1831 from antonio-nino-diaz-arm/an/sccd

Disable processor Cycle Counting in Secure state

Merge pull request #1826 from smaeul/allwinner

allwinner: A few minor improvements

board/rde1edge: rename sgiclarkh to rde1edge

Replace all usage of 'sgiclark' with 'rdn1e1edge' and 'sgiclarkh' with
'rde1edge' as per the updated product names.

Change-Id: I14e9b0332851798531de21d7

board/rde1edge: rename sgiclarkh to rde1edge

Replace all usage of 'sgiclark' with 'rdn1e1edge' and 'sgiclarkh' with
'rde1edge' as per the updated product names.

Change-Id: I14e9b0332851798531de21d70eb54f1e5557a7bd
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

show more ...

board/rdn1edge: rename sgiclarka to rdn1edge

Replace all usage of 'sgiclark' with 'rdn1e1edge' and 'sgiclarka' with
'rdn1edge' as per the updated product names.

Change-Id: Idbc157c73477ec32f507ba2d

board/rdn1edge: rename sgiclarka to rdn1edge

Replace all usage of 'sgiclark' with 'rdn1e1edge' and 'sgiclarka' with
'rdn1edge' as per the updated product names.

Change-Id: Idbc157c73477ec32f507ba2d4a4e907d8813374c
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

show more ...

rpi3: sdhost: SDHost driver improvement

This commit improves the SDHost driver for RPi3 as following:
* Unblock MMC_CMD(17). Using MMC_CMD(17) is more efficient on
block reading.
* In some low

rpi3: sdhost: SDHost driver improvement

This commit improves the SDHost driver for RPi3 as following:
* Unblock MMC_CMD(17). Using MMC_CMD(17) is more efficient on
block reading.
* In some low probability that SEND_OP_COND might results CRC7
error. We can consider that the command runs correctly. We don't
need to retry this command so removing the code for retry.
* Using MMC_BUS_WIDTH_1 as MMC default value to improve the stability.
* Increase the clock to 50Mhz in data mode to speed up the io.
* Change the pull resistors configuration to gain more stability.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>

show more ...

Add workaround for errata 1073348 for Cortex-A76

Concurrent instruction TLB miss and mispredicted return instruction
might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to
prevent this.

Add workaround for errata 1073348 for Cortex-A76

Concurrent instruction TLB miss and mispredicted return instruction
might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to
prevent this.

Change-Id: I2da4f30cd2df3f5e885dd3c4825c557492d1ac58
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

show more ...

Add workaround for errata 1220197 for Cortex-A76

Streaming store under specific conditions might cause deadlock or data
corruption. Set bit 25:24 of CPUECTLR_EL1, which disables write
streaming to t

Add workaround for errata 1220197 for Cortex-A76

Streaming store under specific conditions might cause deadlock or data
corruption. Set bit 25:24 of CPUECTLR_EL1, which disables write
streaming to the L2 to prevent this.

Change-Id: Ib5cabb997b35ada78b27e75787afd610ea606dcf
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

show more ...

Add workaround for errata 1130799 for Cortex-A76

TLBI VAAE1 or TLBI VAALE1 targeting a page within hardware page
aggregated address translation data in the L2 TLB might cause
corruption of address t

Add workaround for errata 1130799 for Cortex-A76

TLBI VAAE1 or TLBI VAALE1 targeting a page within hardware page
aggregated address translation data in the L2 TLB might cause
corruption of address translation data. Set bit 59 of CPUACTLR2_EL1 to
prevent this.

Change-Id: I59f3edea54e87d264e0794f5ca2a8c68a636e586
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

show more ...

Add workaround for errata 790748 for Cortex-A75

Internal timing conditions might cause the CPU to stop processing
interrupts. Set bit 13 of CPUACTLR_EL1 to prevent this.

Change-Id: Ifdd19dbcdb71bb0

Add workaround for errata 790748 for Cortex-A75

Internal timing conditions might cause the CPU to stop processing
interrupts. Set bit 13 of CPUACTLR_EL1 to prevent this.

Change-Id: Ifdd19dbcdb71bb0d9609cab1315c478aaedb03ba
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

show more ...

Add workaround for errata 764081 of Cortex-A75

Implicit Error Synchronization Barrier (IESB) might not be correctly
generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all
expection l

Add workaround for errata 764081 of Cortex-A75

Implicit Error Synchronization Barrier (IESB) might not be correctly
generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all
expection levels.

Change-Id: I2a1a568668a31e4f3f38d0fba1d632ad9939e5ad
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

show more ...

Add workaround for errata 855423 of Cortex-A73

Broadcast maintainance operations might not be correctly synchronized
between cores. Set bit 7 of S3_0_C15_C0_2 to prevent this.

Change-Id: I67fb62c0b

Add workaround for errata 855423 of Cortex-A73

Broadcast maintainance operations might not be correctly synchronized
between cores. Set bit 7 of S3_0_C15_C0_2 to prevent this.

Change-Id: I67fb62c0b458d44320ebaedafcb8495ff26c814b
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

show more ...

plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform

This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A
supports:
- PSCI calls to enable 4 CPU cores
- PSCI mailbox

plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform

This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A
supports:
- PSCI calls to enable 4 CPU cores
- PSCI mailbox calls for FPGA reconfiguration

Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>

show more ...

Merge pull request #1836 from Yann-lms/docs_and_m4

Update documentation for STM32MP1 and add Cortex-M4 support

imx: Configure CAAM job rings master ID for i.MX8MQ

For i.MX8MQ B0 revision the default configuration of JRaMID is not valid
to allow the kernel to use the CAAM job rings. This patch sets the
master

imx: Configure CAAM job rings master ID for i.MX8MQ

For i.MX8MQ B0 revision the default configuration of JRaMID is not valid
to allow the kernel to use the CAAM job rings. This patch sets the
master ID of the Cortex A in the JRaMID registers.

Signed-off-by: Chris Spencer <christopher.spencer@sea.co.uk>

show more ...

Merge pull request #1835 from jts-arm/rename

Apply official names to new Arm Neoverse cores

Merge pull request #1828 from uarif1/master

Introduce Versatile Express FVP platform to arm-trusted-firmware.

Merge pull request #1833 from marex/arm/master/pci-v2.0.0

rcar_gen3: plat: Prevent PCIe hang during L1X config access

stm32mp1: add minimal support for co-processor Cortex-M4

STM32MP1 chip embeds a dual Cortex-A7 and a Cortex-M4.
The support for Cortex-M4 clocks is added when configuring the clock tree.
Some minima

stm32mp1: add minimal support for co-processor Cortex-M4

STM32MP1 chip embeds a dual Cortex-A7 and a Cortex-M4.
The support for Cortex-M4 clocks is added when configuring the clock tree.
Some minimal security features to allow communications between A7 and M4
are also added.

Change-Id: I60417e244a476f60a2758f4969700b2684056665
Signed-off-by: Yann Gautier <yann.gautier@st.com>

show more ...

docs: stm32mp1: add links to documentation

A link to st.com page describing STM32MP1 is added.
Add the information about Cortex-M4 embedded in STM32MP1.
Correct typo for u-boot command.

Change-Id:

docs: stm32mp1: add links to documentation

A link to st.com page describing STM32MP1 is added.
Add the information about Cortex-M4 embedded in STM32MP1.
Correct typo for u-boot command.

Change-Id: Ie900f6ee59461c5e7ad8a8b06854abaf41fca3ce
Signed-off-by: Yann Gautier <yann.gautier@st.com>

show more ...

rcar_gen3: plat: Prevent PCIe hang during L1X config access

In case the PCIe controller receives a L1_Enter_PM DLLP, it will
disable the internal PLLs. The system software cannot predict it
and can

rcar_gen3: plat: Prevent PCIe hang during L1X config access

In case the PCIe controller receives a L1_Enter_PM DLLP, it will
disable the internal PLLs. The system software cannot predict it
and can attempt to perform device config space access across the
PCIe link while the controller is in this transitional state. If
such condition happens, the PCIe controller register access will
trigger ARM64 SError exception.

This patch adds checks for which PCIe controller is enabled,
checks whether the PCIe controller is in such a transitional
state and if so, first completes the transition and then restarts
the instruction which caused the SError.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

show more ...

Merge pull request #1832 from jts-arm/docs

docs: Document romlib design

Merge pull request #1830 from antonio-nino-diaz-arm/an/fix-fw-design

docs: Update documentation about ARMv8.2-TTCNP

Documentation for Versatile Express Fixed Virtual Platforms

This documentation contains information about the boot sequence,
code location and build procedure for fvp_ve platform.

Change-Id: I33990

Documentation for Versatile Express Fixed Virtual Platforms

This documentation contains information about the boot sequence,
code location and build procedure for fvp_ve platform.

Change-Id: I339903f663cc625cfabc75ed8e4accb8b2c3917c
Signed-off-by: Usama Arif <usama.arif@arm.com>

show more ...