meson/gxl: Add tool to create bl31 bootable images

GXL platforms need to have a specific header at the beginning of bl31
image to be able to boot. This adds a tool to create that and calls it at
bui

meson/gxl: Add tool to create bl31 bootable images

GXL platforms need to have a specific header at the beginning of bl31
image to be able to boot. This adds a tool to create that and calls it at
build time.

Signed-off-by: Remi Pommarel <repk@triplefau.lt>

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meson/gxl: Configure and boot SCP

On Amlogic gxl (s905x) SOC, in order to use SCP, bl31 has to send bl30
and bl301 firmware along with their SHA256 hash over scpi.

Signed-off-by: Remi Pommarel <rep

meson/gxl: Configure and boot SCP

On Amlogic gxl (s905x) SOC, in order to use SCP, bl31 has to send bl30
and bl301 firmware along with their SHA256 hash over scpi.

Signed-off-by: Remi Pommarel <repk@triplefau.lt>

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meson/gxl: Add support for SHA256 DMA engine

In order to configure and boot SCP, BL31 has to compute and send
the SHA-256 of the firmware data via scpi. Luckily Amlogic GXL SOC
has a DMA facility th

meson/gxl: Add support for SHA256 DMA engine

In order to configure and boot SCP, BL31 has to compute and send
the SHA-256 of the firmware data via scpi. Luckily Amlogic GXL SOC
has a DMA facility that could be used to offload SHA-256
computations. This adds basic support of this hardware SHA-256
engine.

Signed-off-by: Remi Pommarel <repk@triplefau.lt>

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meson/gxl: Initial port of Amlogic Meson S905x (GXL)

The Amlogic Meson S905x is a SoC with a quad core Arm Cortex-A53 running
at 1.5Ghz. It also contains a Cortex-M3 used as SCP.

This port is a min

meson/gxl: Initial port of Amlogic Meson S905x (GXL)

The Amlogic Meson S905x is a SoC with a quad core Arm Cortex-A53 running
at 1.5Ghz. It also contains a Cortex-M3 used as SCP.

This port is a minimal implementation of BL31 capable of booting
mainline U-Boot and Linux:

- Partial SCPI support.
- Basic PSCI support (CPU_ON, SYSTEM_RESET, SYSTEM_OFF).
- GICv2 driver set up.
- Basic SIP services (read efuse data, enable/disable JTAG).

This port has been tested on a lepotato.

Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Remi Pommarel <repk@triplefau.lt>

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SPM: Ignore empty regions in resource description

Instead of letting the code run until another error is reached, return
early.

Change-Id: I6277a8c65101d3e39b0540099c2a3063584a7dbd
Signed-off-by: A

SPM: Ignore empty regions in resource description

Instead of letting the code run until another error is reached, return
early.

Change-Id: I6277a8c65101d3e39b0540099c2a3063584a7dbd
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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rcar_gen3: plat: Add R-Car V3M support

Add R-Car V3M support. This is based on the original
V3M support patch for Yocto v2.23.1 by Vladimir Barinov.

Signed-off-by: Vladimir Barinov <vladimir.barino

rcar_gen3: plat: Add R-Car V3M support

Add R-Car V3M support. This is based on the original
V3M support patch for Yocto v2.23.1 by Vladimir Barinov.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
---
Marek: Update on top of mainline ATF/master

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Merge pull request #1914 from marex/arm/master/d3draak-v2.0.1

Arm/master/d3draak v2.0.1

rcar_gen3: drivers: qos: Add D3 QoS tables

Add QoS tables for R-Car D3 SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: drivers: pfc: Add D3 PFC tables

Add PFC tables for R-Car D3 SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: drivers: ddr_a: Add D3 DDR init

Add R-Car D3 DDR initialization code. The code is in staging and needs
cleanup, and possibly can even be merged with the E3 init code.

Signed-off-by: Mare

rcar_gen3: drivers: ddr_a: Add D3 DDR init

Add R-Car D3 DDR initialization code. The code is in staging and needs
cleanup, and possibly can even be merged with the E3 init code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

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rcar_gen3: drivers: swdt: Add D3 support

Add WTCNT register configuration for the D3 SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: drivers: scif: Add D3 support

Add SCIF configuration specifics for the D3 SoC, that is detection
of the D3 SoC and SCBRR configuration.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gm

rcar_gen3: drivers: scif: Add D3 support

Add SCIF configuration specifics for the D3 SoC, that is detection
of the D3 SoC and SCBRR configuration.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

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rcar_gen3: drivers: pwrc: Add D3 support

The D3 SoC has one CPU core, just return 1 as a CPU number.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: drivers: rom: Mark NEW table as D3 compatible

Add comment into the ROM driver that the new table is also D3 compatible.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: plat: Add initial D3 support

Add R-Car D3 SoC platform specifics. Driver, PFC, QoS, DDR init code
will be added separately.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: plat: Print DRAM bank size in MiB if below 1 GiB

Print the DRAM bank size in MiB instead of GiB in case the bank size
is smaller than 1 GiB. This prevents printing zeroes on systems with

rcar_gen3: plat: Print DRAM bank size in MiB if below 1 GiB

Print the DRAM bank size in MiB instead of GiB in case the bank size
is smaller than 1 GiB. This prevents printing zeroes on systems with
small DRAM sizes.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

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Merge pull request #1886 from ambroise-arm/av/static-checks

Fix extra compilation warnings

Merge pull request #1913 from marex/arm/master/m3wulcb-v2.0.1

rcar_gen3: plat: Set M3W ULCB DRAM size to 2 GiB

Merge pull request #1898 from hadi-asyrafi/watchdog

intel: Enable watchdog timer on Intel S10 platform

BL1: Fix type consistency

Change function signatures and fix sign-compare warnings.

Change-Id: Iaf755d61e6c54c3dcf4f41aa3c27ea0f6e665fee
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

SPM: Create SPCI auxiliary function

Fix variable shadowing warnings and prevent code duplication.

Change-Id: Idb29cc95d6b6943bc012d7bd430afa0e4a7cbf8c
Signed-off-by: Ambroise Vincent <ambroise.vinc

SPM: Create SPCI auxiliary function

Fix variable shadowing warnings and prevent code duplication.

Change-Id: Idb29cc95d6b6943bc012d7bd430afa0e4a7cbf8c
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

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Remove several warnings reported with W=2

Improved support for W=2 compilation flag by solving some nested-extern
and sign-compare warnings.

The libraries are compiling with warnings (which turn in

Remove several warnings reported with W=2

Improved support for W=2 compilation flag by solving some nested-extern
and sign-compare warnings.

The libraries are compiling with warnings (which turn into errors with
the Werror flag).

Outside of libraries, some warnings cannot be fixed.

Change-Id: I06b1923857f2a6a50e93d62d0274915b268cef05
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

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Remove several warnings reported with W=1

Improved support for W=1 compilation flag by solving missing-prototypes
and old-style-definition warnings.

The libraries are compiling with warnings (which

Remove several warnings reported with W=1

Improved support for W=1 compilation flag by solving missing-prototypes
and old-style-definition warnings.

The libraries are compiling with warnings (which turn into errors with
the Werror flag).

Outside of libraries, some warnings cannot be fixed without heavy
structural changes.

Change-Id: I1668cf99123ac4195c2a6a1d48945f7a64c67f16
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

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Merge pull request #1911 from lmayencourt/lm/update_gcc

doc: Suggest to use the latest version of GCC 8.2

Merge pull request #1912 from pbeesley-arm/pb/spm-reword

doc: Clarify draft status of SPCI and SPRT specs