Improvements in Readme

- Fix broken link to the issue tracker.
- Add contents section to make navigation easier throughout the page.
- Move the link to documentation contents near the top. Where it

Improvements in Readme

- Fix broken link to the issue tracker.
- Add contents section to make navigation easier throughout the page.
- Move the link to documentation contents near the top. Where it was
before could be missed and documentation might seem inaccessible.

Change-Id: I502e4fc0fd312459cda351d30a8781c221625724
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

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sgm: Fix bl2 sources

The weak version of plat_get_mbedtls_heap() was being used.

Change-Id: I6da331a098dd1af5bb64729d5b914cfb74b8869e
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

doc: Clarify cert_create build when USE_TBBR_DEFS=0

The user guide documentation for the cert_create tool needs to
mention that a platform must have a platform_oid.h header file
in order to successf

doc: Clarify cert_create build when USE_TBBR_DEFS=0

The user guide documentation for the cert_create tool needs to
mention that a platform must have a platform_oid.h header file
in order to successfully build the cert_create tool when
USE_TBBR_DEFS is 0.

Change-Id: I77f86a022d207e88a79c97741be3eafbfa0c86f1
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

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plat/sgm: Remove redundant platform_oid.h

This file is used when building the cert_create tool without using
the 'standard' set of Arm OID values as defined in the TBBR
specification (see tbbr_oid.h

plat/sgm: Remove redundant platform_oid.h

This file is used when building the cert_create tool without using
the 'standard' set of Arm OID values as defined in the TBBR
specification (see tbbr_oid.h). This configuration is enabled by
setting USE_TBBR_DEFS to 0 during build.

At the moment this will fail because the header file included by
this file was removed in commit bb41eb7a9dc3 ("cert: move
platform_oid.h to include/tools_share for all platforms"). For
the SGM platform this means that there is no current use for
this file.

Change-Id: I3c82983ada62330f1ab6be6d6c0cf489adabae7b
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

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rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.3

Update the revision number in the revision management file.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-of

rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.3

Update the revision number in the revision management file.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: If8918efad0fcbe6f91b66c0c7438406b1d4fb759

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rcar_gen3: drivers: Change to restore timer counter value at resume

Changed to save and restore cntpct_el0 using memory mapped
register for generic timer when System Suspend and Resume.

Reported by

rcar_gen3: drivers: Change to restore timer counter value at resume

Changed to save and restore cntpct_el0 using memory mapped
register for generic timer when System Suspend and Resume.

Reported by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I40fd9f5434c4d52b320cd1d20322b9b8e4e67155

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rcar_gen3: drivers: pwrc: Add DBSC4 setting before self-refresh mode

Very rarely, LPDDR4 power consumption may not decrease
In self-refresh mode.

This patch fixes the DBSC4 self-refresh mode sequen

rcar_gen3: drivers: pwrc: Add DBSC4 setting before self-refresh mode

Very rarely, LPDDR4 power consumption may not decrease
In self-refresh mode.

This patch fixes the DBSC4 self-refresh mode sequence.

Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Kenji Miyazawa <kenji.miyazawa.xt@renesas.com>
Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Change-Id: I838fa0892b1caf1ecd3f04538b3427e7d971ef59

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rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.2

Update the revision number in the revision management file.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-of

rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.2

Update the revision number in the revision management file.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I239f4d9f58d38515a49fa1a22cece48b59710d15

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rcar_gen3: drivers: ddr: Update DDR setting rev.0.35

[IPL/DDR]
- Update DDR setting rev.0.35.

Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Change-Id: I2b936ca8621ca320cc97353f99240da5f

rcar_gen3: drivers: ddr: Update DDR setting rev.0.35

[IPL/DDR]
- Update DDR setting rev.0.35.

Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Change-Id: I2b936ca8621ca320cc97353f99240da5f24781f7

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rcar_gen3: drivers: qos: change subslot cycle

Subslot cycle from 132 to 126 as default setting.
Subslot cycle from 264 to 252.

[IPL/QoS]
- Update H3 Ver.2.0 QoS setting rev.0.21.
- Update H3 Ver

rcar_gen3: drivers: qos: change subslot cycle

Subslot cycle from 132 to 126 as default setting.
Subslot cycle from 264 to 252.

[IPL/QoS]
- Update H3 Ver.2.0 QoS setting rev.0.21.
- Update H3 Ver.3.0 QoS setting rev.0.11.
- Update M3 Ver.1.1 QoS setting rev.0.19.
- Update M3 Ver.3.0 QoS setting rev.0.02.
- Update M3N Ver.1.1 QoS setting rev.0.09.

Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I52b1bf880163ce03065dc8933d7f193e45cfd9a5

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rcar_gen3: drivers: board: Add new board revision for H3ULCB

Board Revision[2:0]
3'b000 Rev1.0 OB
3'b001 Rev1.0 CE
3'b010 Rev2.0 [New]

Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
Cha

rcar_gen3: drivers: board: Add new board revision for H3ULCB

Board Revision[2:0]
3'b000 Rev1.0 OB
3'b001 Rev1.0 CE
3'b010 Rev2.0 [New]

Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
Change-Id: I0f109cddc95eca78aea34c7149e70f14e2f1620b

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rcar_gen3: plat: Change periodic write DQ training option.

Periodic write DQ training available as default.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yo

rcar_gen3: plat: Change periodic write DQ training option.

Periodic write DQ training available as default.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I649cfe538e4e2c7e19145ce7d1938ce4361b2529

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plat: allwinner: common: use r_wdog instead of wdog

Some Allwinner H6 has a broken watchdog that doesn't
make the soc reboot.

Use the R_WATCHDOG instead.

Signed-off-by: Clément Péron <peron.clem@g

plat: allwinner: common: use r_wdog instead of wdog

Some Allwinner H6 has a broken watchdog that doesn't
make the soc reboot.

Use the R_WATCHDOG instead.

Signed-off-by: Clément Péron <peron.clem@gmail.com>
Change-Id: Ie95cc30a80ed517b60b30d6bc2e655a1b53f18ba

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hikey960: Fix race condition between hotplug and idles

From the hotplug testing on Hikey960, in some case cores fail to become
online in the system. When some cores are hotplugged off, if other
core

hikey960: Fix race condition between hotplug and idles

From the hotplug testing on Hikey960, in some case cores fail to become
online in the system. When some cores are hotplugged off, if other
cores in the same cluster enter into CPU idle states at the meantime,
the cluster will be powered off. This introduces the state machine
malfunction in the power controller, thus when hotplug on the core
afterwards, it fails to boot up the core because the power controller
thinks the cluster is powered on.

This patch is to avoid race condition between hotplug and idles by
preventing cluster power off when some of cores in the cluster are
hotplugged off, if all cores in the same cluster are hotplugged off,
the cluster can be powered off.

Change-Id: Ib2feeb093357c70409a3536cb4f9da9b504fdcbe
Signed-off-by: Wei Yu <yuwei3@hisilicon.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>

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cache_helpers.s:fix mixed tabs and spaces

Change-Id: I8b7c7888d09200410e1a1c11a070c94dd8013ea7
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>

Add note about erratum 814220 for A7

On Cortex-A7 an L2 set/way cache maintenance operation can overtake
an L1 set/way cache maintenance operation. The mitigation for this is
to use a `DSB` instruct

Add note about erratum 814220 for A7

On Cortex-A7 an L2 set/way cache maintenance operation can overtake
an L1 set/way cache maintenance operation. The mitigation for this is
to use a `DSB` instruction before changing cache. The cache cleaning
code happens to already be doing this, so only a comment was added.

Change-Id: Ia1ffb8ca8b6bbbba422ed6f6818671ef9fe02d90
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>

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Merge "aarch32: Allow compiling with soft-float toolchain" into integration

Merge "services/spm: Fix service UUID lookup" into integration

Merge "cpus: Fix Cortex-A12 MIDR mask" into integration

services/spm: Fix service UUID lookup

The spm_sp_get_by_uuid() function is used to look up the secure
partition that provides a given service.

Within this function, memcmp() is used to compare the

services/spm: Fix service UUID lookup

The spm_sp_get_by_uuid() function is used to look up the secure
partition that provides a given service.

Within this function, memcmp() is used to compare the service
UUIDs but it uses the size of the rdsvc->uuid pointer instead of
the size of its content (missing dereference). This means that only
a partial comparison is performed as UUIDs are 128 bits in length and
rdsvc->uuid is a uint32_t typed pointer.

Instead, use the size of the array pointed to by the svc_uuid parameter,
which will be the full 128 bits, for the comparison.

Change-Id: I258fb0cca3bf19f97b8f2a4c133981647cd050e4
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

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Merge "Add support for Cortex-A76AE CPU" into integration

Checkpatch: Style fix

Change-Id: I0cb9f0db1ef3491f55c038a10db5a88d37e89697
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>

Merge changes from topic "jh/cotdesc" into integration

* changes:
Document changes to auth-framework
cot-desc: optimise memory further
Reduce memory needed for CoT description

Add support for Cortex-A76AE CPU

Change-Id: I0a81f4ea94d41245cd5150de341b51fc70babffe
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

Document changes to auth-framework

The data structures in the auth-framework were changed by the previous
patch, and need to be updated.

Change-Id: Icfad2ac688d03d32aa93e45f930a375abbc164a9
Signed-

Document changes to auth-framework

The data structures in the auth-framework were changed by the previous
patch, and need to be updated.

Change-Id: Icfad2ac688d03d32aa93e45f930a375abbc164a9
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>

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