1 /* 2 * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdint.h> 8 9 #include <common/debug.h> 10 #include <lib/mmio.h> 11 12 #include "qos_init.h" 13 #include "qos_common.h" 14 #include "qos_reg.h" 15 #if RCAR_LSI == RCAR_AUTO 16 #include "H3/qos_init_h3_v10.h" 17 #include "H3/qos_init_h3_v11.h" 18 #include "H3/qos_init_h3_v20.h" 19 #include "H3/qos_init_h3_v30.h" 20 #include "M3/qos_init_m3_v10.h" 21 #include "M3/qos_init_m3_v11.h" 22 #include "M3/qos_init_m3_v30.h" 23 #include "M3N/qos_init_m3n_v10.h" 24 #include "V3M/qos_init_v3m.h" 25 #endif 26 #if RCAR_LSI == RCAR_H3 /* H3 */ 27 #include "H3/qos_init_h3_v10.h" 28 #include "H3/qos_init_h3_v11.h" 29 #include "H3/qos_init_h3_v20.h" 30 #include "H3/qos_init_h3_v30.h" 31 #endif 32 #if RCAR_LSI == RCAR_H3N /* H3 */ 33 #include "H3/qos_init_h3n_v30.h" 34 #endif 35 #if RCAR_LSI == RCAR_M3 /* M3 */ 36 #include "M3/qos_init_m3_v10.h" 37 #include "M3/qos_init_m3_v11.h" 38 #include "M3/qos_init_m3_v30.h" 39 #endif 40 #if RCAR_LSI == RCAR_M3N /* M3N */ 41 #include "M3N/qos_init_m3n_v10.h" 42 #endif 43 #if RCAR_LSI == RCAR_V3M /* V3M */ 44 #include "V3M/qos_init_v3m.h" 45 #endif 46 #if RCAR_LSI == RCAR_E3 /* E3 */ 47 #include "E3/qos_init_e3_v10.h" 48 #endif 49 #if RCAR_LSI == RCAR_D3 /* D3 */ 50 #include "D3/qos_init_d3.h" 51 #endif 52 53 /* Product Register */ 54 #define PRR 0xFFF00044U 55 #define PRR_PRODUCT_MASK 0x00007F00U 56 #define PRR_CUT_MASK 0x000000FFU 57 #define PRR_PRODUCT_H3 0x00004F00U /* R-Car H3 */ 58 #define PRR_PRODUCT_M3 0x00005200U /* R-Car M3 */ 59 #define PRR_PRODUCT_V3M 0x00005400U /* R-Car V3M */ 60 #define PRR_PRODUCT_M3N 0x00005500U /* R-Car M3N */ 61 #define PRR_PRODUCT_E3 0x00005700U /* R-Car E3 */ 62 #define PRR_PRODUCT_D3 0x00005800U /* R-Car D3 */ 63 #define PRR_PRODUCT_10 0x00U 64 #define PRR_PRODUCT_11 0x01U 65 #define PRR_PRODUCT_20 0x10U 66 #define PRR_PRODUCT_21 0x11U 67 #define PRR_PRODUCT_30 0x20U 68 69 #if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3) && (RCAR_LSI != RCAR_V3M) 70 71 #define DRAM_CH_CNT 0x04 72 uint32_t qos_init_ddr_ch; 73 uint8_t qos_init_ddr_phyvalid; 74 #endif 75 76 #define PRR_PRODUCT_ERR(reg) \ 77 do { \ 78 ERROR("LSI Product ID(PRR=0x%x) QoS " \ 79 "initialize not supported.\n", reg); \ 80 panic(); \ 81 } while (0) 82 83 #define PRR_CUT_ERR(reg) \ 84 do { \ 85 ERROR("LSI Cut ID(PRR=0x%x) QoS " \ 86 "initialize not supported.\n", reg); \ 87 panic(); \ 88 } while (0) 89 90 void rcar_qos_init(void) 91 { 92 uint32_t reg; 93 #if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3) && (RCAR_LSI != RCAR_V3M) 94 uint32_t i; 95 96 qos_init_ddr_ch = 0; 97 qos_init_ddr_phyvalid = get_boardcnf_phyvalid(); 98 for (i = 0; i < DRAM_CH_CNT; i++) { 99 if ((qos_init_ddr_phyvalid & (1 << i))) { 100 qos_init_ddr_ch++; 101 } 102 } 103 #endif 104 105 reg = mmio_read_32(PRR); 106 #if (RCAR_LSI == RCAR_AUTO) || RCAR_LSI_CUT_COMPAT 107 switch (reg & PRR_PRODUCT_MASK) { 108 case PRR_PRODUCT_H3: 109 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) 110 switch (reg & PRR_CUT_MASK) { 111 case PRR_PRODUCT_10: 112 qos_init_h3_v10(); 113 break; 114 case PRR_PRODUCT_11: 115 qos_init_h3_v11(); 116 break; 117 case PRR_PRODUCT_20: 118 qos_init_h3_v20(); 119 break; 120 case PRR_PRODUCT_30: 121 default: 122 qos_init_h3_v30(); 123 break; 124 } 125 #elif (RCAR_LSI == RCAR_H3N) 126 switch (reg & PRR_CUT_MASK) { 127 case PRR_PRODUCT_30: 128 default: 129 qos_init_h3n_v30(); 130 break; 131 } 132 #else 133 PRR_PRODUCT_ERR(reg); 134 #endif 135 break; 136 case PRR_PRODUCT_M3: 137 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3) 138 switch (reg & PRR_CUT_MASK) { 139 case PRR_PRODUCT_10: 140 qos_init_m3_v10(); 141 break; 142 case PRR_PRODUCT_21: /* M3 Cut 13 */ 143 qos_init_m3_v11(); 144 break; 145 case PRR_PRODUCT_30: /* M3 Cut 30 */ 146 default: 147 qos_init_m3_v30(); 148 break; 149 } 150 #else 151 PRR_PRODUCT_ERR(reg); 152 #endif 153 break; 154 case PRR_PRODUCT_M3N: 155 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N) 156 switch (reg & PRR_CUT_MASK) { 157 case PRR_PRODUCT_10: 158 default: 159 qos_init_m3n_v10(); 160 break; 161 } 162 #else 163 PRR_PRODUCT_ERR(reg); 164 #endif 165 break; 166 case PRR_PRODUCT_V3M: 167 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3M) 168 switch (reg & PRR_CUT_MASK) { 169 case PRR_PRODUCT_10: 170 case PRR_PRODUCT_20: 171 default: 172 qos_init_v3m(); 173 break; 174 } 175 #else 176 PRR_PRODUCT_ERR(reg); 177 #endif 178 break; 179 case PRR_PRODUCT_E3: 180 #if (RCAR_LSI == RCAR_E3) 181 switch (reg & PRR_CUT_MASK) { 182 case PRR_PRODUCT_10: 183 default: 184 qos_init_e3_v10(); 185 break; 186 } 187 #else 188 PRR_PRODUCT_ERR(reg); 189 #endif 190 break; 191 case PRR_PRODUCT_D3: 192 #if (RCAR_LSI == RCAR_D3) 193 switch (reg & PRR_CUT_MASK) { 194 case PRR_PRODUCT_10: 195 default: 196 qos_init_d3(); 197 break; 198 } 199 #else 200 PRR_PRODUCT_ERR(reg); 201 #endif 202 break; 203 default: 204 PRR_PRODUCT_ERR(reg); 205 break; 206 } 207 #else 208 #if RCAR_LSI == RCAR_H3 /* H3 */ 209 #if RCAR_LSI_CUT == RCAR_CUT_10 210 /* H3 Cut 10 */ 211 if ((PRR_PRODUCT_H3 | PRR_PRODUCT_10) 212 != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) { 213 PRR_PRODUCT_ERR(reg); 214 } 215 qos_init_h3_v10(); 216 #elif RCAR_LSI_CUT == RCAR_CUT_11 217 /* H3 Cut 11 */ 218 if ((PRR_PRODUCT_H3 | PRR_PRODUCT_11) 219 != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) { 220 PRR_PRODUCT_ERR(reg); 221 } 222 qos_init_h3_v11(); 223 #elif RCAR_LSI_CUT == RCAR_CUT_20 224 /* H3 Cut 20 */ 225 if ((PRR_PRODUCT_H3 | PRR_PRODUCT_20) 226 != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) { 227 PRR_PRODUCT_ERR(reg); 228 } 229 qos_init_h3_v20(); 230 #else 231 /* H3 Cut 30 or later */ 232 if ((PRR_PRODUCT_H3) 233 != (reg & (PRR_PRODUCT_MASK))) { 234 PRR_PRODUCT_ERR(reg); 235 } 236 qos_init_h3_v30(); 237 #endif 238 #elif RCAR_LSI == RCAR_H3N /* H3 */ 239 /* H3N Cut 30 or later */ 240 if ((PRR_PRODUCT_H3) 241 != (reg & (PRR_PRODUCT_MASK))) { 242 PRR_PRODUCT_ERR(reg); 243 } 244 qos_init_h3n_v30(); 245 #elif RCAR_LSI == RCAR_M3 /* M3 */ 246 #if RCAR_LSI_CUT == RCAR_CUT_10 247 /* M3 Cut 10 */ 248 if ((PRR_PRODUCT_M3 | PRR_PRODUCT_10) 249 != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) { 250 PRR_PRODUCT_ERR(reg); 251 } 252 qos_init_m3_v10(); 253 #elif RCAR_LSI_CUT == RCAR_CUT_11 254 /* M3 Cut 11 */ 255 if ((PRR_PRODUCT_M3 | PRR_PRODUCT_20) 256 != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) { 257 PRR_PRODUCT_ERR(reg); 258 } 259 qos_init_m3_v11(); 260 #elif RCAR_LSI_CUT == RCAR_CUT_13 261 /* M3 Cut 13 */ 262 if ((PRR_PRODUCT_M3 | PRR_PRODUCT_21) 263 != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) { 264 PRR_PRODUCT_ERR(reg); 265 } 266 qos_init_m3_v11(); 267 #else 268 /* M3 Cut 30 or later */ 269 if ((PRR_PRODUCT_M3) 270 != (reg & (PRR_PRODUCT_MASK))) { 271 PRR_PRODUCT_ERR(reg); 272 } 273 qos_init_m3_v30(); 274 #endif 275 #elif RCAR_LSI == RCAR_M3N /* M3N */ 276 /* M3N Cut 10 or later */ 277 if ((PRR_PRODUCT_M3N) 278 != (reg & (PRR_PRODUCT_MASK))) { 279 PRR_PRODUCT_ERR(reg); 280 } 281 qos_init_m3n_v10(); 282 #elif RCAR_LSI == RCAR_V3M /* V3M */ 283 /* V3M Cut 10 or later */ 284 if ((PRR_PRODUCT_V3M) 285 != (reg & (PRR_PRODUCT_MASK))) { 286 PRR_PRODUCT_ERR(reg); 287 } 288 qos_init_v3m(); 289 #elif RCAR_LSI == RCAR_D3 /* D3 */ 290 /* D3 Cut 10 or later */ 291 if ((PRR_PRODUCT_D3) 292 != (reg & (PRR_PRODUCT_MASK))) { 293 PRR_PRODUCT_ERR(reg); 294 } 295 qos_init_d3(); 296 #elif RCAR_LSI == RCAR_E3 /* E3 */ 297 /* E3 Cut 10 or later */ 298 if ((PRR_PRODUCT_E3) 299 != (reg & (PRR_PRODUCT_MASK))) { 300 PRR_PRODUCT_ERR(reg); 301 } 302 qos_init_e3_v10(); 303 #else 304 #error "Don't have QoS initialize routine(Unknown chip)." 305 #endif 306 #endif 307 } 308 309 #if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3) && (RCAR_LSI != RCAR_V3M) 310 uint32_t get_refperiod(void) 311 { 312 uint32_t refperiod = QOSWT_WTSET0_CYCLE; 313 314 #if (RCAR_LSI == RCAR_AUTO) || RCAR_LSI_CUT_COMPAT 315 uint32_t reg; 316 317 reg = mmio_read_32(PRR); 318 switch (reg & PRR_PRODUCT_MASK) { 319 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) 320 case PRR_PRODUCT_H3: 321 switch (reg & PRR_CUT_MASK) { 322 case PRR_PRODUCT_10: 323 case PRR_PRODUCT_11: 324 break; 325 case PRR_PRODUCT_20: 326 case PRR_PRODUCT_30: 327 default: 328 refperiod = REFPERIOD_CYCLE; 329 break; 330 } 331 break; 332 #elif (RCAR_LSI == RCAR_H3N) 333 case PRR_PRODUCT_H3: 334 switch (reg & PRR_CUT_MASK) { 335 case PRR_PRODUCT_30: 336 default: 337 refperiod = REFPERIOD_CYCLE; 338 break; 339 } 340 break; 341 #endif 342 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3) 343 case PRR_PRODUCT_M3: 344 switch (reg & PRR_CUT_MASK) { 345 case PRR_PRODUCT_10: 346 break; 347 case PRR_PRODUCT_20: /* M3 Cut 11 */ 348 case PRR_PRODUCT_21: /* M3 Cut 13 */ 349 case PRR_PRODUCT_30: /* M3 Cut 30 */ 350 default: 351 refperiod = REFPERIOD_CYCLE; 352 break; 353 } 354 break; 355 #endif 356 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N) 357 case PRR_PRODUCT_M3N: 358 refperiod = REFPERIOD_CYCLE; 359 break; 360 #endif 361 default: 362 break; 363 } 364 #elif RCAR_LSI == RCAR_H3 365 #if RCAR_LSI_CUT == RCAR_CUT_10 366 /* H3 Cut 10 */ 367 #elif RCAR_LSI_CUT == RCAR_CUT_11 368 /* H3 Cut 11 */ 369 #else 370 /* H3 Cut 20 */ 371 /* H3 Cut 30 or later */ 372 refperiod = REFPERIOD_CYCLE; 373 #endif 374 #elif RCAR_LSI == RCAR_H3N 375 /* H3N Cut 30 or later */ 376 refperiod = REFPERIOD_CYCLE; 377 #elif RCAR_LSI == RCAR_M3 378 #if RCAR_LSI_CUT == RCAR_CUT_10 379 /* M3 Cut 10 */ 380 #else 381 /* M3 Cut 11 */ 382 /* M3 Cut 13 */ 383 /* M3 Cut 30 or later */ 384 refperiod = REFPERIOD_CYCLE; 385 #endif 386 #elif RCAR_LSI == RCAR_M3N /* for M3N */ 387 refperiod = REFPERIOD_CYCLE; 388 #endif 389 390 return refperiod; 391 } 392 #endif 393 394 void rcar_qos_dbsc_setting(struct rcar_gen3_dbsc_qos_settings *qos, 395 unsigned int qos_size, bool dbsc_wren) 396 { 397 int i; 398 399 /* Register write enable */ 400 if (dbsc_wren) 401 io_write_32(DBSC_DBSYSCNT0, 0x00001234U); 402 403 for (i = 0; i < qos_size; i++) 404 io_write_32(qos[i].reg, qos[i].val); 405 406 /* Register write protect */ 407 if (dbsc_wren) 408 io_write_32(DBSC_DBSYSCNT0, 0x00000000U); 409 } 410