feat(gicv5): add support for building with gicv5

The Generic Interrupt Controller v5 (GICv5) is the next generation of
Arm interrupt controllers. It is a clean slate design and has native
support fo

feat(gicv5): add support for building with gicv5

The Generic Interrupt Controller v5 (GICv5) is the next generation of
Arm interrupt controllers. It is a clean slate design and has native
support for the latest Armv9 features. As such it is entirely backwards
incompatible with GICv3/v4.

This patch adds the necessary boilerplate to select a build with GICv5.
The GIC has always had two parts. BL31 deals directly with the CPU
interface while platform code is responsible for managing the IRI. In v5
this split is formalised and the CPU interface, FEAT_GCIE, may be
implemented on its own. So reflect this split in our code with
ENABLE_FEAT_GCIE which only affects BL31 and the GICv5 IRI lies in the
generic GIC driver.

No actual functionality yet.

Change-Id: I97a0c3ba708877c213e50e7ef148e3412aa2af90
Co-developed-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(sdei): resolve coverity error for SDEI GIC" into integration

Merge "feat(psci): add API to get number of CPUs currently in ON state" into integration

Merge changes from topic "mb/misc-drtm-fixes" into integration

* changes:
fix(drtm): measure and record the DLME EP offset instead of absolute address
fix(drtm): set correct max region mask for

Merge changes from topic "mb/misc-drtm-fixes" into integration

* changes:
fix(drtm): measure and record the DLME EP offset instead of absolute address
fix(drtm): set correct max region mask for DMA protection to 0xFFFF
fix(drtm): correct PROTECT_MEM_REGION value as per DRTM specification
fix(drtm): add event name data for separator event entries

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fix(fvp): workaround when PCIe 2 region is not present in DTB

This patch applies a workaround to the RMM manifest when the DT
does not specify the 2nd PCIe region. As per FVP RevC memory map [1],
th

fix(fvp): workaround when PCIe 2 region is not present in DTB

This patch applies a workaround to the RMM manifest when the DT
does not specify the 2nd PCIe region. As per FVP RevC memory map [1],
there are 2 PCIe regions but the upstream FVP DT sourced from
kernel.org does not have this region specified. Temporarily
workaround this issue in FVP platform layer till the upstream DT is
fixed.

Note that the DT in `fdts` folder of TF-A source tree already has the
2 regions specified.

[1] https://developer.arm.com/documentation/100966/1101-00/Programming-Reference-for-Base-FVPs/Base---memory

Change-Id: If220e2dbeff00a1bf6eccadbb0ebb661b9c5e529
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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fix(nxp-crypto): restricts generating nxp_mkvb via ns-world

Master-key-verification-blob (MKVB) value generated on request from
the secure world, is same to the MKVB value generated on request from

fix(nxp-crypto): restricts generating nxp_mkvb via ns-world

Master-key-verification-blob (MKVB) value generated on request from
the secure world, is same to the MKVB value generated on request from
Normal world. Leading to the leak og MKVB to non-secure world.

Fix to prevent MKVB generation for requests originating from non-secure
world.
- For non-secure world, this SMC is return failure.

Additional fix for bound-check before continuing to generate the MKVB.

Change-Id: I9940b4dfe33289c2d57595a2a08acff29a12c974
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>

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feat(fvp): give bootargs on all configs

Linux needs bootargs on all configs. SPM_MM was left as CI wouldn't pass
but the error is unrelated and now works too.

Change-Id: I78874344b5972ae3ff136da5a8

feat(fvp): give bootargs on all configs

Linux needs bootargs on all configs. SPM_MM was left as CI wouldn't pass
but the error is unrelated and now works too.

Change-Id: I78874344b5972ae3ff136da5a8f119d376d53ba2
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(sdei): resolve coverity error for SDEI GIC

Fix the following issues from Coverity check:

*** CID 463142: Memory - illegal accesses (INTEGER_OVERFLOW)
/services/std_svc/sdei/sdei_event.c: 79 i

fix(sdei): resolve coverity error for SDEI GIC

Fix the following issues from Coverity check:

*** CID 463142: Memory - illegal accesses (INTEGER_OVERFLOW)
/services/std_svc/sdei/sdei_event.c: 79 in get_event_entry_target_pe()

*** CID 463141: Memory - illegal accesses (NEGATIVE_RETURNS)
/services/std_svc/sdei/sdei_intr_mgmt.c: 64 in sdei_is_target_pe_masked()

Change-Id: I0f2928a6405f091b1ea988a43428d7032ee4c136
Signed-off-by: Mark Dykes <mark.dykes@arm.com>

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Merge changes Ie23e8ae5,I4d142cb0,I528a1117 into integration

* changes:
feat(mt8189): add pmic driver
feat(mt8189): add PWRAP driver
feat(mt8189): add SPMI driver

Merge "fix(rme): enable support for FEAT_D128 on Realm world" into integration

Merge "build(commitlint): treat wrong scopes as error" into integration

feat(memmap): add summary command to memory map script

This patch adds a `summary` command, invoked with:

poetry run memory summary <map-file>

This command is capable of producing a summary tabl

feat(memmap): add summary command to memory map script

This patch adds a `summary` command, invoked with:

poetry run memory summary <map-file>

This command is capable of producing a summary table, similar to the
footprint command, or an HTML flame-graph representing the size of ELF
image sections.

When specified with `-o` (`--old`), an old GNU map file is used as a
past state and subtracted from the GNU map file specified by
`<map-file>` to annotate printed information with additional size
deltas.

Note that many bootloaders include alignment padding and will align to
a page size. To exclude this alignment-padding from the summary, use the
`-e` switch.

For example:

$ poetry run memory summary bl1.map -e -d 1
| Module | .text | .data | .bss |
|-----------|--------------|----------|-----------|
| bl1 | 32616(+24) | 2217(+0) | 11175(+0) |
| lib | 55932(+2060) | 40(+0) | 10628(+0) |
| Subtotals | 88548(+2084) | 2257(+0) | 21803(+0) |
Total Static RAM memory (data + bss): 24060(+0) bytes
Total Flash memory (text + data): 90805(+2084) bytes

Change-Id: Id0bc157d09e654f89730dfbe318fa5f820e9f18d
Co-authored-by: Chris Kay <chris.kay@arm.com>
Signed-off-by: Chris Kay <chris.kay@arm.com>
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

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Merge "fix(libc): add missing curly braces" into integration

fix(console): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a

fix(console): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
Variable type has been updated from uint8_t to uint32_t to avoid
assigning a value to an object with a narrower essential type.

Change-Id: I2c901eb837a3042b5a097b3c7b516bb6cd813289
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(console): typecast operands to match data type

This corrects the MISRA violation C2012-10.1:
Operands shall not be of an inappropriate essential type.
The condition is explicitly checked against

fix(console): typecast operands to match data type

This corrects the MISRA violation C2012-10.1:
Operands shall not be of an inappropriate essential type.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: Ie78d91f0f79804797648ef996fb208d3ee1698dd
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge "feat(errata): implement workaround for DSU-120 erratum 2900952" into integration

fix(rme): enable support for FEAT_D128 on Realm world

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I9a4431038968a260e1a4998d8a4f84a07768db74

build(commitlint): treat wrong scopes as error

The commitlint checker treats scopes that are not listed in the
changelog.yaml file as warnings. This is then usually overlooked, as
commitlint checker

build(commitlint): treat wrong scopes as error

The commitlint checker treats scopes that are not listed in the
changelog.yaml file as warnings. This is then usually overlooked, as
commitlint checker passes with warnings in CI and some patches with
wrong scope can be merged. The maintainers doing the release note will
then have to deal with those patches manually.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ica5f581ce7b8c1adbe35f5ab3e6870d9a07807fd

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feat(errata): implement workaround for DSU-120 erratum 2900952

DSU Erratum 2900952 is a Cat B erratum that applies to some
DSU-120 implementations of revision r2p0 and is fixed in r2p1.
This erratum

feat(errata): implement workaround for DSU-120 erratum 2900952

DSU Erratum 2900952 is a Cat B erratum that applies to some
DSU-120 implementations of revision r2p0 and is fixed in r2p1.
This erratum is fixed in certain implementations of r2p0 which can be
determined by reading the IMP_CLUSTERREVIDR_EL1[1] register field
where a set bit indicates that the erratum is fixed in this part.

The workaround is to set the CLUSTERACTLR_EL1 bits [21:20] to 0x3
which ignores CBusy from the system interconnect and
setting CLUSTERACTLR_EL1 bit [8] to 1 to assert CBusy from DSU to
all the cores when DSU is busy.

SDEN: https://developer.arm.com/documentation/SDEN-2453103/1200/?lang=en

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I87aa440ab5c35121aff703032f5cf7a62d0b0bb4

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fix(sptool): handle load-address-relative-offset property

If the SP manifest contains load-address-relative-offset then the script
failed to generate the sp_list_fragment.dts file because that line

fix(sptool): handle load-address-relative-offset property

If the SP manifest contains load-address-relative-offset then the script
failed to generate the sp_list_fragment.dts file because that line was
also added to the load_address_lines list.
This commit fixes this issue: a line is only added to the list if the
property name is exactly "load-address", without a following '-'
character.

Change-Id: I1fd2006d37d9cc1864af31576e60565a7bce6023
Signed-off-by: Bence Balogh <bence.balogh@arm.com>

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Merge "fix(mt8195): fix variable may be used uninitialized error" into integration

Merge "fix(mt8188): fix variable may be used uninitialized error" into integration

Merge changes from topic "validate node ID in PM events" into integration

* changes:
fix(versal2): validate Node ID in PM callback events
fix(xilinx): validate Node ID in PM callback events
fi

Merge changes from topic "validate node ID in PM events" into integration

* changes:
fix(versal2): validate Node ID in PM callback events
fix(xilinx): validate Node ID in PM callback events
fix(xilinx): add macro to extract node class from node ID

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Merge "fix(allwinner): fix variable may be used uninitialized error" into integration

feat(psci): add API to get number of CPUs currently in ON state

Introduce a new PSCI helper function `psci_num_cpus_running_on_safe()`
to return the number of CPUs that are currently in the ON state

feat(psci): add API to get number of CPUs currently in ON state

Introduce a new PSCI helper function `psci_num_cpus_running_on_safe()`
to return the number of CPUs that are currently in the ON state.
This API locks the PSCI power state data to ensure consistency and
is safe to call in concurrent environments.

This utility can assist components that need to reason about system
CPU activity or coordinate operations based on active CPUs.

Change-Id: Ie15aa4bd393a5f01e7cd80ae8a9b28707fde7c53
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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