History log of /rk3399_ARM-atf/ (Results 12901 – 12925 of 18314)
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c9e40ec531-May-2019 Paul Beesley <paul.beesley@arm.com>

Merge changes from topic "jts/docs" into integration

* changes:
Removing IRC related info from the documentation
Further fixes to documentation links

008c843c31-May-2019 John Tsichritzis <john.tsichritzis@arm.com>

Removing IRC related info from the documentation

Change-Id: I5cf8c70a304bf5869cbeb12fa8d39171cff48ebd
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

e9eed3f130-May-2019 Paul Beesley <paul.beesley@arm.com>

Merge "rockchip: drop rockchip-specific imported linker symbols for bl31" into integration

c4e4df3517-May-2019 Paul Beesley <paul.beesley@arm.com>

doc: Enable automatic labels for page titles

Automatic labelling of document titles is a prerequisite for
converting the format of cross-document links. Sphinx will
generate (via the enabled extensi

doc: Enable automatic labels for page titles

Automatic labelling of document titles is a prerequisite for
converting the format of cross-document links. Sphinx will
generate (via the enabled extension) a hidden link target for
each document title and this can be referred to later, from
another page, to link to the target.

The plugin options being used require Sphinx >= 2.0.0 so a
requirements.txt file has been added. This file is used with
the pip package manager for Python so that the correct
dependencies are installed.

Change-Id: Ic2049db5804aa4a6447608ba4299de958ce0a87d
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

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f6ad51c828-May-2019 John Tsichritzis <john.tsichritzis@arm.com>

Further fixes to documentation links

Change-Id: Ib021c721652d96f6c06ea18741f19a72bba1d00f
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

8416741729-May-2019 Paul Beesley <paul.beesley@arm.com>

Merge "Cortex-A55: workarounds for errata 1221012" into integration

3e6945e929-May-2019 Heiko Stuebner <heiko@sntech.de>

rockchip: drop rockchip-specific imported linker symbols for bl31

In the rockchip bl31 setup the __RO_START__ and __RO_END__ symbols are
currently imported into special BL31_RO_* constants while the

rockchip: drop rockchip-specific imported linker symbols for bl31

In the rockchip bl31 setup the __RO_START__ and __RO_END__ symbols are
currently imported into special BL31_RO_* constants while the general
code also imports them as BL_CODE_BASE and BL_CODE_END.

So we can just use the general symbols and can drop the duplication.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: Ibf1b48ad80bed897247a1690a32711030479262d

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5a40810429-May-2019 Paul Beesley <paul.beesley@arm.com>

Merge "Beautify "make help"" into integration

bac571ac29-May-2019 Paul Beesley <paul.beesley@arm.com>

Merge "Makefile: Add default warning flags" into integration

9af07df028-May-2019 Ambroise Vincent <ambroise.vincent@arm.com>

Cortex-A55: workarounds for errata 1221012

The workaround is added to the Cortex-A55 cpu specific file. The
workaround is disabled by default and have to be explicitly enabled by
the platform integr

Cortex-A55: workarounds for errata 1221012

The workaround is added to the Cortex-A55 cpu specific file. The
workaround is disabled by default and have to be explicitly enabled by
the platform integrator.

Change-Id: I3e6fd10df6444122a8ee7d08058946ff1cc912f8
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

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4d384eb428-May-2019 Soby Mathew <soby.mathew@arm.com>

Merge "plat: imx8m: Add the aipstz init to config peripheral access" into integration

68b8ab0b28-May-2019 Soby Mathew <soby.mathew@arm.com>

Merge changes from topic "for-upstream" into integration

* changes:
ti: k3: common: Set L2 latency on A72 cores
ti: k3: common: Add support for J721E

89a4d26928-May-2019 John Tsichritzis <john.tsichritzis@arm.com>

Merge "Fix documentation links" into integration

566d15e828-May-2019 John Tsichritzis <john.tsichritzis@arm.com>

Fix documentation links

Change-Id: Ic09e74f22b43fba51ee17cd02b5e1dc5d8e0bb63
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

508a48bb24-May-2019 Paul Beesley <paul.beesley@arm.com>

Merge "Add support for Branch Target Identification" into integration

c0e9d43324-May-2019 Paul Beesley <paul.beesley@arm.com>

Merge changes from topic "jts/docs" into integration

* changes:
Docs fixes
Update security documentation

9fc5963924-May-2019 Alexei Fedorov <Alexei.Fedorov@arm.com>

Add support for Branch Target Identification

This patch adds the functionality needed for platforms to provide
Branch Target Identification (BTI) extension, introduced to AArch64
in Armv8.5-A by add

Add support for Branch Target Identification

This patch adds the functionality needed for platforms to provide
Branch Target Identification (BTI) extension, introduced to AArch64
in Armv8.5-A by adding BTI instruction used to mark valid targets
for indirect branches. The patch sets new GP bit [50] to the stage 1
Translation Table Block and Page entries to denote guarded EL3 code
pages which will cause processor to trap instructions in protected
pages trying to perform an indirect branch to any instruction other
than BTI.
BTI feature is selected by BRANCH_PROTECTION option which supersedes
the previous ENABLE_PAUTH used for Armv8.3-A Pointer Authentication
and is disabled by default. Enabling BTI requires compiler support
and was tested with GCC versions 9.0.0, 9.0.1 and 10.0.0.
The assembly macros and helpers are modified to accommodate the BTI
instruction.
This is an experimental feature.
Note. The previous ENABLE_PAUTH build option to enable PAuth in EL3
is now made as an internal flag and BRANCH_PROTECTION flag should be
used instead to enable Pointer Authentication.
Note. USE_LIBROM=1 option is currently not supported.

Change-Id: Ifaf4438609b16647dc79468b70cd1f47a623362e
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

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0029657624-May-2019 Ambroise Vincent <ambroise.vincent@arm.com>

Makefile: Add default warning flags

The flags are taken from the different warning levels of the build
system when they do not generate any error with the current upstreamed
platforms.

Change-Id: I

Makefile: Add default warning flags

The flags are taken from the different warning levels of the build
system when they do not generate any error with the current upstreamed
platforms.

Change-Id: Ia70cff83bedefb6d2f0dd266394ef77fe47e7f65
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

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a16fd37f24-May-2019 John Tsichritzis <john.tsichritzis@arm.com>

Docs fixes

1) Fix links in "about" page
2) Put back the "contents" page with adjusted links

Change-Id: Id09140b91df5cf0a275149801d05d8cfeeda1c6e
Signed-off-by: John Tsichritzis <john.tsichritzis@ar

Docs fixes

1) Fix links in "about" page
2) Put back the "contents" page with adjusted links

Change-Id: Id09140b91df5cf0a275149801d05d8cfeeda1c6e
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

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55f1405921-May-2019 John Tsichritzis <john.tsichritzis@arm.com>

Update security documentation

1) Replace references to "Arm Trusted Firmware" with "TF-A"
2) Update issue tracker link

Change-Id: I12d827d49f6cc34e46936d7f7ccf44e32b26a0bd
Signed-off-by: John Tsich

Update security documentation

1) Replace references to "Arm Trusted Firmware" with "TF-A"
2) Update issue tracker link

Change-Id: I12d827d49f6cc34e46936d7f7ccf44e32b26a0bd
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

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bbb24f6121-May-2019 John Tsichritzis <john.tsichritzis@arm.com>

Introduce BTI support in ROMLIB

When TF-A is compiled with BTI enabled, the branches in the ROMLIB
jumptable must be preceded by a "bti j" instruction.

Moreover, when the additional "bti" instructi

Introduce BTI support in ROMLIB

When TF-A is compiled with BTI enabled, the branches in the ROMLIB
jumptable must be preceded by a "bti j" instruction.

Moreover, when the additional "bti" instruction is inserted, the
jumptable entries have a distance of 8 bytes between them instead of 4.
Hence, the wrappers are also modified accordinly.

If TF-A is compiled without BTI enabled, the ROMLIB jumptable and
wrappers are generated as before.

Change-Id: Iaa59897668f8e59888d39046233300c2241d8de7
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

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7c23126c21-May-2019 John Tsichritzis <john.tsichritzis@arm.com>

Beautify "make help"

Changes to make the help text a bit more readable:
1) The "usage" part is now a one-liner
2) The supported platforms list is printed separately

Change-Id: I93e48a6cf1d28f0ef9f3

Beautify "make help"

Changes to make the help text a bit more readable:
1) The "usage" part is now a one-liner
2) The supported platforms list is printed separately

Change-Id: I93e48a6cf1d28f0ef9f3db16ce17725e4dff33c9
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

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570948d323-May-2019 Sandrine Bailleux <sandrine.bailleux@arm.com>

Merge "plat/meson/gxl: BL31: remove BL2 dependency" into integration

ced1711223-May-2019 Sandrine Bailleux <sandrine.bailleux@arm.com>

Merge changes from topic "pb/sphinx-doc" into integration

* changes:
doc: Use proper note and warning annotations
doc: Refactor contributor acknowledgements
doc: Reorganise images and update l

Merge changes from topic "pb/sphinx-doc" into integration

* changes:
doc: Use proper note and warning annotations
doc: Refactor contributor acknowledgements
doc: Reorganise images and update links
doc: Set correct syntax highlighting style
doc: Add minimal glossary
doc: Remove per-page contents lists
doc: Make checkpatch ignore rst files
doc: Format security advisory titles and headings
doc: Reformat platform port documents
doc: Normalise section numbering and headings
doc: Reword document titles

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Makefile
docs/acknowledgements.rst
docs/change-log.rst
docs/components/arm-sip-service.rst
docs/components/exception-handling.rst
docs/components/firmware-update.rst
docs/components/platform-interrupt-controller-API.rst
docs/components/ras.rst
docs/components/romlib-design.rst
docs/components/sdei.rst
docs/components/secure-partition-manager-design.rst
docs/components/spd/index.rst
docs/components/spd/tlk-dispatcher.rst
docs/components/spd/trusty-dispatcher.rst
docs/components/xlat-tables-lib-v2-design.rst
docs/conf.py
docs/design/auth-framework.rst
docs/design/cpu-specific-build-macros.rst
docs/design/firmware-design.rst
docs/design/interrupt-framework-design.rst
docs/design/psci-pd-tree.rst
docs/design/reset-design.rst
docs/design/trusted-board-boot.rst
docs/getting_started/image-terminology.rst
docs/getting_started/porting-guide.rst
docs/getting_started/psci-lib-integration-guide.rst
docs/getting_started/rt-svc-writers-guide.rst
docs/getting_started/user-guide.rst
docs/global_substitutions.txt
docs/glossary.rst
docs/index.rst
docs/maintainers.rst
docs/perf/psci-performance-juno.rst
docs/plat/allwinner.rst
docs/plat/fvp_ve.rst
docs/plat/imx8.rst
docs/plat/imx8m.rst
docs/plat/index.rst
docs/plat/intel-stratix10.rst
docs/plat/ls1043a.rst
docs/plat/meson-gxbb.rst
docs/plat/meson-gxl.rst
docs/plat/mt8183.rst
docs/plat/nvidia-tegra.rst
docs/plat/qemu.rst
docs/plat/rcar-gen3.rst
docs/plat/rockchip.rst
docs/plat/rpi3.rst
docs/plat/socionext-uniphier.rst
docs/plat/stm32mp1.rst
docs/plat/synquacer.rst
docs/plat/ti-k3.rst
docs/plat/warp7.rst
docs/plat/xilinx-versal.rst
docs/plat/xilinx-zynqmp.rst
docs/process/coding-guidelines.rst
docs/process/contributing.rst
docs/process/index.rst
docs/process/platform-compatibility-policy.rst
docs/process/release-information.rst
docs/process/security.rst
docs/resources/diagrams/Makefile
docs/resources/diagrams/default_reset_code.png
docs/resources/diagrams/draw.io/ehf.svg
docs/resources/diagrams/draw.io/ehf.xml
docs/resources/diagrams/draw.io/ras.svg
docs/resources/diagrams/draw.io/ras.xml
docs/resources/diagrams/fwu_flow.png
docs/resources/diagrams/fwu_states.png
docs/resources/diagrams/int_handling.dia
docs/resources/diagrams/non-sec-int-handling.png
docs/resources/diagrams/plantuml/plantuml_to_svg.sh
docs/resources/diagrams/plantuml/sdei_explicit_dispatch.puml
docs/resources/diagrams/plantuml/sdei_explicit_dispatch.svg
docs/resources/diagrams/plantuml/sdei_general.puml
docs/resources/diagrams/plantuml/sdei_general.svg
docs/resources/diagrams/psci-suspend-sequence.png
docs/resources/diagrams/reset_code_flow.dia
docs/resources/diagrams/reset_code_no_boot_type_check.png
docs/resources/diagrams/reset_code_no_checks.png
docs/resources/diagrams/reset_code_no_cpu_check.png
docs/resources/diagrams/romlib_design.dia
docs/resources/diagrams/romlib_design.png
docs/resources/diagrams/romlib_wrapper.dia
docs/resources/diagrams/romlib_wrapper.png
docs/resources/diagrams/rt-svc-descs-layout.png
docs/resources/diagrams/sec-int-handling.png
docs/resources/diagrams/secure_sw_stack_sp.png
docs/resources/diagrams/secure_sw_stack_tos.png
docs/resources/diagrams/xlat_align.dia
docs/resources/diagrams/xlat_align.png
docs/security_advisories/security-advisory-tfv-1.rst
docs/security_advisories/security-advisory-tfv-2.rst
docs/security_advisories/security-advisory-tfv-3.rst
docs/security_advisories/security-advisory-tfv-4.rst
docs/security_advisories/security-advisory-tfv-5.rst
docs/security_advisories/security-advisory-tfv-6.rst
docs/security_advisories/security-advisory-tfv-7.rst
docs/security_advisories/security-advisory-tfv-8.rst
license.rst
1665bcd023-May-2019 Sandrine Bailleux <sandrine.bailleux@arm.com>

Merge "drivers: scmi: scmi_sq: Modify wrong payload length" into integration

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