| 37b70031 | 04-Jul-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
arm: Shorten the Firmware Update (FWU) process
The watchdog is configured with a default value of 256 seconds in order
to implement the Trusted Board Boot Requirements.
For the FVP and Juno platfor
arm: Shorten the Firmware Update (FWU) process
The watchdog is configured with a default value of 256 seconds in order
to implement the Trusted Board Boot Requirements.
For the FVP and Juno platforms, the FWU process relies on a watchdog
reset. In order to automate the test of FWU, the length of this process
needs to be as short as possible. Instead of waiting for those 4 minutes
to have a reset by the watchdog, tell it to reset immediately.
There are no side effects as the value of the watchdog's load register
resets to 0xFFFFFFFF.
Tested on Juno.
Change-Id: Ib1aea80ceddc18ff1e0813a5b98dd141ba8a3ff2
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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| 53f3751b | 23-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "Cortex_hercules: Introduce preliminary cpu support" into integration |
| 1d7dc63c | 23-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "Enable MTE support unilaterally for Normal World" into integration |
| d8210dc6 | 09-Jul-2019 |
Imre Kis <imre.kis@arm.com> |
Romlib makefile refactoring and script rewriting
The features of the previously existing gentbl, genvar and genwrappers
scripts were reimplemented in the romlib_generator.py Python script.
This resu
Romlib makefile refactoring and script rewriting
The features of the previously existing gentbl, genvar and genwrappers
scripts were reimplemented in the romlib_generator.py Python script.
This resulted in more readable and maintainable code and the script
introduces additional features that help dependency handling in
makefiles. The assembly templates were separated from the script logic
and were collected in the 'templates' directory.
The targets and their dependencies were reorganized in the makefile and
the dependency handling of included index files is possible now.
Incremental build is available in case of modifying the index files.
Signed-off-by: Imre Kis <imre.kis@arm.com>
Change-Id: I79f65fab9dc5c70d1f6fc8f57b2a3009bf842dc5
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| c424b91e | 22-Jul-2019 |
Imre Kis <imre.kis@arm.com> |
Fix BL31 crash reporting on AArch64 only machines
The AArch32 system registers are not listed if the platform supports
AArch64 only.
Change-Id: I087a10ae6e7cad1bb52775a344635dbac1f12679
Signed-off-
Fix BL31 crash reporting on AArch64 only machines
The AArch32 system registers are not listed if the platform supports
AArch64 only.
Change-Id: I087a10ae6e7cad1bb52775a344635dbac1f12679
Signed-off-by: Imre Kis <imre.kis@arm.com>
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| b514ee86 | 19-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "intel: Adds support for Agilex platform" into integration |
| 59e3df6e | 19-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "doc: Complete the storage abstraction layer doc" into integration |
| b852d229 | 25-May-2019 |
Julius Werner <jwerner@chromium.org> |
Introduce lightweight BL platform parameter library
This patch adds some common helper code to support a lightweight
platform parameter passing framework between BLs that has already been
used on Ro
Introduce lightweight BL platform parameter library
This patch adds some common helper code to support a lightweight
platform parameter passing framework between BLs that has already been
used on Rockchip platforms but is more widely useful to others as well.
It can be used as an implementation for the SoC firmware configuration
file mentioned in the docs, and is primarily intended for platforms
that only require a handful of values to be passed and want to get by
without a libfdt dependency. Parameters are stored in a linked list and
the parameter space is split in generic and vendor-specific parameter
types. Generic types will be handled by this code whereas
vendor-specific types have to be handled by a vendor-specific handler
function that gets passed in.
Change-Id: If3413d44e86b99d417294ce8d33eb2fc77a6183f
Signed-off-by: Julius Werner <jwerner@chromium.org>
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| dbeace10 | 15-Jul-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
doc: Complete the storage abstraction layer doc
Add uml sequence and class diagram to illustrate the behavior of the
storage abstraction layer.
Change-Id: I338262729f8034cc3d3eea1d0ce19cca973a91bb
doc: Complete the storage abstraction layer doc
Add uml sequence and class diagram to illustrate the behavior of the
storage abstraction layer.
Change-Id: I338262729f8034cc3d3eea1d0ce19cca973a91bb
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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| 2f11d548 | 27-Jun-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: Adds support for Agilex platform
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib2ad2068abdf0b204c5cb021ea919581adaca4ef |
| 7871fff2 | 17-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "backtrace: Strip PAC field when PAUTH is enabled" into integration |
| b8b31ad0 | 09-Jul-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
backtrace: Strip PAC field when PAUTH is enabled
When pointer authentication is enabled, the LR value saved on the stack
contains a Pointer Authentication Code (PAC). It must be stripped to
retrieve
backtrace: Strip PAC field when PAUTH is enabled
When pointer authentication is enabled, the LR value saved on the stack
contains a Pointer Authentication Code (PAC). It must be stripped to
retrieve the return address.
The PAC field is stored on the high bits of the address and defined as:
- PAC field = Xn[54:bottom_PAC_bit], when address tagging is used.
- PAC field = Xn[63:56, 54:bottom_PAC_bit], without address tagging.
With bottom_PAC_bit = 64 - TCR_ELx.TnSZ
Change-Id: I21d804e58200dfeca1da4c2554690bed5d191936
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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| 7a8ef89f | 17-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "plat/arm: Introduce A5 DesignStart platform." into integration |
| b8c691e9 | 17-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "doc: Generate PlantUML diagrams automatically" into integration |
| df5bd3bf | 17-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "console: update skeleton" into integration |
| 7cdd55af | 17-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes I68941876,Ib7961812,I758661d3,I4f3e3812,I9b26b838, ... into integration
* changes:
rcar_gen3: drivers: ddr-a: Fix E3 DDR init coding style
rcar_gen3: drivers: ddr-a: Pass ddrBackup
Merge changes I68941876,Ib7961812,I758661d3,I4f3e3812,I9b26b838, ... into integration
* changes:
rcar_gen3: drivers: ddr-a: Fix E3 DDR init coding style
rcar_gen3: drivers: ddr-a: Pass ddrBackup around
rcar_gen3: drivers: ddr-a: Inline ddr_init_e3.h
rcar_gen3: drivers: ddr-a: Fix V3M DDR init coding style
rcar_gen3: drivers: ddr-a: Fix D3 DDR init coding style
rcar_gen3: drivers: ddr-a: Replace {Read,Write}Reg_32() with mmio_{read,write}_32()
rcar_gen3: drivers: ddr-a: Unify register definitions
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| f7694165 | 17-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "rcar_gen3: drivers: ddr: Replace BITn with BIT(n) macro" into integration |
| 936072ed | 13-Jun-2019 |
Jun Nie <jun.nie@linaro.org> |
plat: imx7: Add PicoPi iMX7D basic support
The PicoPi iMX7D is a 2 board development board consisting of
a System-on-Module and a carrier baseboard and optimized for
the Internet-of-Things (IoT).
T
plat: imx7: Add PicoPi iMX7D basic support
The PicoPi iMX7D is a 2 board development board consisting of
a System-on-Module and a carrier baseboard and optimized for
the Internet-of-Things (IoT).
This patch add basic support to this board.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Reviewed-by: Louis Mayencourt <louis.mayencourt@arm.com>
Change-Id: I009d85819c4f73b7063aab73d0f6ee74e6ef3fc4
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| c5937f2d | 13-Jun-2019 |
Jun Nie <jun.nie@linaro.org> |
plat: imx7: refactor code for reuse
For the iMX7 SOCs, part of the code for platform
setup implementation can be reused and made
common for all these SoCs. This patch extracts
the common part for re
plat: imx7: refactor code for reuse
For the iMX7 SOCs, part of the code for platform
setup implementation can be reused and made
common for all these SoCs. This patch extracts
the common part for reuse.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Change-Id: I42fd4167e6903416df96a0159a046abf3896e878
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| 294f9ef9 | 14-May-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
Cortex_hercules: Introduce preliminary cpu support
Change-Id: Iab767e9937f5c6c8150953fcdc3b37e8ee83fa63
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> |
| 3c7dcdac | 14-Jul-2019 |
Remi Pommarel <repk@triplefau.lt> |
marvell/a3700: Prevent SError accessing PCIe link while it is down
When the link goes down (e.g. during a retrain), accessing the device
configuration space can trigger an ARM64 SError interrupt. Su
marvell/a3700: Prevent SError accessing PCIe link while it is down
When the link goes down (e.g. during a retrain), accessing the device
configuration space can trigger an ARM64 SError interrupt. Such
conditions cannot be predicted, so to avoid a crash the SError is
ignored.
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Change-Id: I2b1fd3296cc1c88b9ca1fe21c0924cb324eed58d
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| 6e9e15b0 | 14-Jul-2019 |
Remi Pommarel <repk@triplefau.lt> |
marvell: Switch to xlat_tables_v2
Use v2 xlat tables library instead of v1 for marvell platforms.
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Change-Id: I838a6a878a8353e84eea9529721761b478943f
marvell: Switch to xlat_tables_v2
Use v2 xlat tables library instead of v1 for marvell platforms.
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Change-Id: I838a6a878a8353e84eea9529721761b478943f0a
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| 00c7d5ac | 18-Jun-2019 |
Usama Arif <usama.arif@arm.com> |
plat/arm: Introduce A5 DesignStart platform.
This patch adds support for Cortex-A5 FVP for the
DesignStart program. DesignStart aims at providing
low cost and fast access to Arm IP.
Currently with
plat/arm: Introduce A5 DesignStart platform.
This patch adds support for Cortex-A5 FVP for the
DesignStart program. DesignStart aims at providing
low cost and fast access to Arm IP.
Currently with this patch only the primary CPU is booted
and the rest of them wait for an interrupt.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I3a2281ce6de2402dda4610a89939ed53aa045fab
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| 52e91081 | 31-May-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
console: update skeleton
Update the skeleton implementation of the console interface.
The 32 bit version was outdated and has been copied from the 64 bit
version.
Change-Id: Ib3e4eb09402ffccb1a30c
console: update skeleton
Update the skeleton implementation of the console interface.
The 32 bit version was outdated and has been copied from the 64 bit
version.
Change-Id: Ib3e4eb09402ffccb1a30c703a53829a7bf064dfe
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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| d0d0f171 | 16-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "jc/shift-overflow" into integration
* changes:
Enable -Wshift-overflow=2 to check for undefined shift behavior
Update base code to not rely on undefined overflow behavi
Merge changes from topic "jc/shift-overflow" into integration
* changes:
Enable -Wshift-overflow=2 to check for undefined shift behavior
Update base code to not rely on undefined overflow behaviour
Update hisilicon drivers to not rely on undefined overflow behaviour
Update synopsys drivers to not rely on undefined overflow behaviour
Update imx platform to not rely on undefined overflow behaviour
Update mediatek platform to not rely on undefined overflow behaviour
Update layerscape platform to not rely on undefined overflow behaviour
Update intel platform to not rely on undefined overflow behaviour
Update rockchip platform to not rely on undefined overflow behaviour
Update renesas platform to not rely on undefined overflow behaviour
Update meson platform to not rely on undefined overflow behaviour
Update marvell platform to not rely on undefined overflow behaviour
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