xref: /rk3399_ARM-atf/plat/rpi/rpi4/include/platform_def.h (revision f5cb15b0c886afaa41c5d3dad8e859b6a41f76ab) 
1 /*
2  * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef PLATFORM_DEF_H
8 #define PLATFORM_DEF_H
9 
10 #include <arch.h>
11 #include <common/tbbr/tbbr_img_def.h>
12 #include <lib/utils_def.h>
13 #include <plat/common/common_def.h>
14 
15 #include "rpi_hw.h"
16 
17 /* Special value used to verify platform parameters from BL2 to BL31 */
18 #define RPI3_BL31_PLAT_PARAM_VAL	ULL(0x0F1E2D3C4B5A6978)
19 
20 #define PLATFORM_STACK_SIZE		ULL(0x1000)
21 
22 #define PLATFORM_MAX_CPUS_PER_CLUSTER	U(4)
23 #define PLATFORM_CLUSTER_COUNT		U(1)
24 #define PLATFORM_CLUSTER0_CORE_COUNT	PLATFORM_MAX_CPUS_PER_CLUSTER
25 #define PLATFORM_CORE_COUNT		PLATFORM_CLUSTER0_CORE_COUNT
26 
27 #define RPI4_PRIMARY_CPU		U(0)
28 
29 #define PLAT_MAX_PWR_LVL		MPIDR_AFFLVL1
30 #define PLAT_NUM_PWR_DOMAINS		(PLATFORM_CLUSTER_COUNT + \
31 					 PLATFORM_CORE_COUNT)
32 
33 #define PLAT_MAX_RET_STATE		U(1)
34 #define PLAT_MAX_OFF_STATE		U(2)
35 
36 /* Local power state for power domains in Run state. */
37 #define PLAT_LOCAL_STATE_RUN		U(0)
38 /* Local power state for retention. Valid only for CPU power domains */
39 #define PLAT_LOCAL_STATE_RET		U(1)
40 /*
41  * Local power state for OFF/power-down. Valid for CPU and cluster power
42  * domains.
43  */
44 #define PLAT_LOCAL_STATE_OFF		U(2)
45 
46 /*
47  * Macros used to parse state information from State-ID if it is using the
48  * recommended encoding for State-ID.
49  */
50 #define PLAT_LOCAL_PSTATE_WIDTH		U(4)
51 #define PLAT_LOCAL_PSTATE_MASK		((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1)
52 
53 /*
54  * Some data must be aligned on the biggest cache line size in the platform.
55  * This is known only to the platform as it might have a combination of
56  * integrated and external caches.
57  */
58 #define CACHE_WRITEBACK_SHIFT		U(6)
59 #define CACHE_WRITEBACK_GRANULE		(U(1) << CACHE_WRITEBACK_SHIFT)
60 
61 /*
62  * Partition memory into secure ROM, non-secure DRAM, secure "SRAM", and
63  * secure DRAM. Note that this is all actually DRAM with different names,
64  * there is no Secure RAM in the Raspberry Pi 4.
65  */
66 #if RPI3_USE_UEFI_MAP
67 #define SEC_ROM_BASE			ULL(0x00000000)
68 #define SEC_ROM_SIZE			ULL(0x00010000)
69 
70 /* FIP placed after ROM to append it to BL1 with very little padding. */
71 #define PLAT_RPI3_FIP_BASE		ULL(0x00020000)
72 #define PLAT_RPI3_FIP_MAX_SIZE		ULL(0x00010000)
73 
74 /* Reserve 2M of secure SRAM and DRAM, starting at 2M */
75 #define SEC_SRAM_BASE			ULL(0x00200000)
76 #define SEC_SRAM_SIZE			ULL(0x00100000)
77 
78 #define SEC_DRAM0_BASE			ULL(0x00300000)
79 #define SEC_DRAM0_SIZE			ULL(0x00100000)
80 
81 /* Windows on ARM requires some RAM at 4M */
82 #define NS_DRAM0_BASE			ULL(0x00400000)
83 #define NS_DRAM0_SIZE			ULL(0x00C00000)
84 #else
85 #define SEC_ROM_BASE			ULL(0x00000000)
86 #define SEC_ROM_SIZE			ULL(0x00020000)
87 
88 /* FIP placed after ROM to append it to BL1 with very little padding. */
89 #define PLAT_RPI3_FIP_BASE		ULL(0x00020000)
90 #define PLAT_RPI3_FIP_MAX_SIZE		ULL(0x001E0000)
91 
92 /* We have 16M of memory reserved starting at 256M */
93 #define SEC_SRAM_BASE			ULL(0x10000000)
94 #define SEC_SRAM_SIZE			ULL(0x00100000)
95 
96 #define SEC_DRAM0_BASE			ULL(0x10100000)
97 #define SEC_DRAM0_SIZE			ULL(0x00F00000)
98 /* End of reserved memory */
99 
100 #define NS_DRAM0_BASE			ULL(0x11000000)
101 #define NS_DRAM0_SIZE			ULL(0x01000000)
102 #endif /* RPI3_USE_UEFI_MAP */
103 
104 /*
105  * BL33 entrypoint.
106  */
107 #define PLAT_RPI3_NS_IMAGE_OFFSET	NS_DRAM0_BASE
108 #define PLAT_RPI3_NS_IMAGE_MAX_SIZE	NS_DRAM0_SIZE
109 
110 /*
111  * I/O registers.
112  */
113 #define DEVICE0_BASE			RPI_IO_BASE
114 #define DEVICE0_SIZE			RPI_IO_SIZE
115 
116 /*
117  * TF-A lives in SRAM, partition it here
118  */
119 #define SHARED_RAM_BASE			SEC_SRAM_BASE
120 #define SHARED_RAM_SIZE			ULL(0x00001000)
121 
122 #define BL_RAM_BASE			(SHARED_RAM_BASE + SHARED_RAM_SIZE)
123 #define BL_RAM_SIZE			(SEC_SRAM_SIZE - SHARED_RAM_SIZE)
124 
125 /*
126  * Mailbox to control the secondary cores. All secondary cores are held in a
127  * wait loop in cold boot. To release them perform the following steps (plus
128  * any additional barriers that may be needed):
129  *
130  *     uint64_t *entrypoint = (uint64_t *)PLAT_RPI3_TM_ENTRYPOINT;
131  *     *entrypoint = ADDRESS_TO_JUMP_TO;
132  *
133  *     uint64_t *mbox_entry = (uint64_t *)PLAT_RPI3_TM_HOLD_BASE;
134  *     mbox_entry[cpu_id] = PLAT_RPI3_TM_HOLD_STATE_GO;
135  *
136  *     sev();
137  */
138 #define PLAT_RPI3_TRUSTED_MAILBOX_BASE	SHARED_RAM_BASE
139 
140 /* The secure entry point to be used on warm reset by all CPUs. */
141 #define PLAT_RPI3_TM_ENTRYPOINT		PLAT_RPI3_TRUSTED_MAILBOX_BASE
142 #define PLAT_RPI3_TM_ENTRYPOINT_SIZE	ULL(8)
143 
144 /* Hold entries for each CPU. */
145 #define PLAT_RPI3_TM_HOLD_BASE		(PLAT_RPI3_TM_ENTRYPOINT + \
146 					 PLAT_RPI3_TM_ENTRYPOINT_SIZE)
147 #define PLAT_RPI3_TM_HOLD_ENTRY_SIZE	ULL(8)
148 #define PLAT_RPI3_TM_HOLD_SIZE		(PLAT_RPI3_TM_HOLD_ENTRY_SIZE * \
149 					 PLATFORM_CORE_COUNT)
150 
151 #define PLAT_RPI3_TRUSTED_MAILBOX_SIZE	(PLAT_RPI3_TM_ENTRYPOINT_SIZE + \
152 					 PLAT_RPI3_TM_HOLD_SIZE)
153 
154 #define PLAT_RPI3_TM_HOLD_STATE_WAIT	ULL(0)
155 #define PLAT_RPI3_TM_HOLD_STATE_GO	ULL(1)
156 
157 /*
158  * BL31 specific defines.
159  *
160  * Put BL31 at the top of the Trusted SRAM. BL31_BASE is calculated using the
161  * current BL31 debug size plus a little space for growth.
162  */
163 #define PLAT_MAX_BL31_SIZE		ULL(0x20000)
164 
165 #define BL31_BASE			ULL(0x1000)
166 #define BL31_LIMIT			ULL(0x100000)
167 #define BL31_PROGBITS_LIMIT		ULL(0x100000)
168 
169 #define SEC_SRAM_ID			0
170 #define SEC_DRAM_ID			1
171 
172 /*
173  * Other memory-related defines.
174  */
175 #define PLAT_PHY_ADDR_SPACE_SIZE	(ULL(1) << 32)
176 #define PLAT_VIRT_ADDR_SPACE_SIZE	(ULL(1) << 32)
177 
178 #define MAX_MMAP_REGIONS		8
179 #define MAX_XLAT_TABLES			4
180 
181 #define MAX_IO_DEVICES			U(3)
182 #define MAX_IO_HANDLES			U(4)
183 
184 #define MAX_IO_BLOCK_DEVICES		U(1)
185 
186 /*
187  * Serial-related constants.
188  */
189 #define PLAT_RPI3_UART_BASE		RPI3_MINI_UART_BASE
190 #define PLAT_RPI3_UART_BAUDRATE		ULL(115200)
191 
192 /*
193  * System counter
194  */
195 #define SYS_COUNTER_FREQ_IN_TICKS	ULL(54000000)
196 
197 #endif /* PLATFORM_DEF_H */
198