Tegra194: enable SMMU

Enable smmu by setting ENABLE_SMMU_DEVICE to 1.

Change-Id: I9135071b257a166fa6082b7fe409bcd315cf6838
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

Tegra194: add support for multiple SMMU devices

This patch adds support for all three SMMU devices present on the SoC.

The following changes have been done:
Add SMMU devices to the memory map

Tegra194: add support for multiple SMMU devices

This patch adds support for all three SMMU devices present on the SoC.

The following changes have been done:
Add SMMU devices to the memory map
Update register read and write functions

Change-Id: I0007b496d2ae7264f4fa9f605d4b0a15fa747a0f
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

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Tegra194: add SMMU and mc_sid support

Define mc sid and txn override regs and sec cfgs.
Create array for mc sid override regs and sec config that is
used to initialize mc.
Add smmu ctx regs array to

Tegra194: add SMMU and mc_sid support

Define mc sid and txn override regs and sec cfgs.
Create array for mc sid override regs and sec config that is
used to initialize mc.
Add smmu ctx regs array to hold register values during suspend.

Change-Id: I7b265710a9ec2be7dea050058bce65c614772c78
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

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Tegra194: psci: support for 64-bit TZDRAM base

This patch fixes the variable width to store the TZDRAM base
address used to resume from System Suspend.

Change-Id: I3c18eb844963f39f91b5ac45e3709f335

Tegra194: psci: support for 64-bit TZDRAM base

This patch fixes the variable width to store the TZDRAM base
address used to resume from System Suspend.

Change-Id: I3c18eb844963f39f91b5ac45e3709f3354bcda0c
Signed-off-by: Steven Kao <skao@nvidia.com>

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Tegra194: base commit for the platform

This patch creates the base commit for the Tegra194 platform, from
Tegra186 code base.

Change-Id: I1c77e4984f7ff39655f3fb79633d13d533707ede
Signed-off-by: Var

Tegra194: base commit for the platform

This patch creates the base commit for the Tegra194 platform, from
Tegra186 code base.

Change-Id: I1c77e4984f7ff39655f3fb79633d13d533707ede
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Revert "Tegra: Add support for fake system suspend"

This reverts commit c41df8fda84b9bc56bbb2347fb902f64b1bb557e

Fake system suspend relies on software running on EL3
to trigger a warm reset.

Reve

Revert "Tegra: Add support for fake system suspend"

This reverts commit c41df8fda84b9bc56bbb2347fb902f64b1bb557e

Fake system suspend relies on software running on EL3
to trigger a warm reset.

Revert enabling fake system suspend, as the software
running on El3 is not allowed to trigger a warm reset.

Change-Id: I6035f2a7bcb0a4ad50a62c5bc5239226c625ee5e
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>

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Fix white space errors + remove #if defined

Fix a few white space errors and remove #if defined in workaround
for N1 Errata 1542419.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
C

Fix white space errors + remove #if defined

Fix a few white space errors and remove #if defined in workaround
for N1 Errata 1542419.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I07ac5a2fd50cd63de53c06e3d0f8262871b62fad

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Merge "Update TF-A version to 2.2" into integration

Merge "Update change log for v2.2 Release" into integration

Merge "Update release-information for v2.2 Release" into integration

Merge "doc: Final, pre-release fixes and updates" into integration

doc: Final, pre-release fixes and updates

A small set of misc changes to ensure correctness before the v2.2
release tagging.

Change-Id: I888840b9483ea1a1633d204fbbc0f9594072101e
Signed-off-by: Paul

doc: Final, pre-release fixes and updates

A small set of misc changes to ensure correctness before the v2.2
release tagging.

Change-Id: I888840b9483ea1a1633d204fbbc0f9594072101e
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

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Update release-information for v2.2 Release

Removed deprecated interfaces that have been removed from the TF-A
project, updated the deprecated list with new deprecations for v2.2
Release, added upco

Update release-information for v2.2 Release

Removed deprecated interfaces that have been removed from the TF-A
project, updated the deprecated list with new deprecations for v2.2
Release, added upcoming release information, remove mentions of PR from
github.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Change-Id: I2b59d351cde9860ad0dcb6520a8bd2827ad403cf

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Merge "doc: Expand contact information in About section" into integration

doc: Expand contact information in About section

Giving a bit more background information about the issue tracker
and mailing lists.

Change-Id: I68921d54e3113d348f1e16c685f74d32df2ca19f
Signed-off-

doc: Expand contact information in About section

Giving a bit more background information about the issue tracker
and mailing lists.

Change-Id: I68921d54e3113d348f1e16c685f74d32df2ca19f
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

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Merge "doc: Move platform list to the Platform Ports index page" into integration

Merge "doc: Move "About" content from index.rst to a new chapter" into integration

Update change log for v2.2 Release

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I53a7706016539e7de7fdbe87b786d99665bbe1d8

doc: Move platform list to the Platform Ports index page

The list of upstream platforms on the index page is growing
quite long, especially with all the FVP variants being listed
individually.

This

doc: Move platform list to the Platform Ports index page

The list of upstream platforms on the index page is growing
quite long, especially with all the FVP variants being listed
individually.

This patch leverages the "Platform Ports" chapter in the docs
table of contents to condense this information. Almost all
platform ports now have documentation, so the table of
contents serves as the list of upstream platforms by itself.

For those upstream platforms that do not have corresponding
documentation, the top-level "Platform Ports" page mentions
them individually. It also mentions each Arm FVP, just as
the index page did before.

Note that there is an in-progress patch that creates new
platform port documentation for the Arm Juno and Arm FVP
platforms, so this list of "other platforms" will soon be
reduced further as those platforms become part of the
table of contents as well.

Change-Id: I6b1eab8cba71a599d85a6e22553a34b07f213268
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

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doc: Move "About" content from index.rst to a new chapter

The index.rst page is now the primary landing page for the TF-A
documentation. It contains quite a lot of content these days,
including:

-

doc: Move "About" content from index.rst to a new chapter

The index.rst page is now the primary landing page for the TF-A
documentation. It contains quite a lot of content these days,
including:

- The project purpose and general intro
- A list of functionality
- A list of planned functionality
- A list of supported platforms
- "Getting started" links to other documents
- Contact information for raising issues

This patch creates an "About" chapter in the table
of contents and moves some content there. In order,
the above listed content:

- Stayed where it is. This is the right place for it.
- Moved to About->Features
- Moved to About->Features (in subsection)
- Stayed where it is. Moved in a later patch.
- Was expanded in-place
- Moved to About->Contact

Change-Id: I254bb87560fd09140b9e485cf15246892aa45943
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

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plat/arm: use Aff3 bits also to validate mpidr

There are some platforms which uses MPIDR Affinity level 3 for storing
extra affinity information e.g. N1SDP uses it for keeping chip id in a
multichip

plat/arm: use Aff3 bits also to validate mpidr

There are some platforms which uses MPIDR Affinity level 3 for storing
extra affinity information e.g. N1SDP uses it for keeping chip id in a
multichip setup, for such platforms MPIDR validation should not fail.

This patch adds Aff3 bits also as part of mpidr validation mask, for
platforms which does not uses Aff3 will not have any impact as these
bits will be all zeros.

Change-Id: Ia8273972fa7948fdb11708308d0239d2dc4dfa85
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

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Merge "xlat_table_v2: Fix enable WARMBOOT_ENABLE_DCACHE_EARLY config" into integration

Merge "Replace deprecated __ASSEMBLY__ macro with __ASSEMBLER__" into integration

Disable stack protection explicitly

Explicitly disable stack protection via the "-fno-stack-protector"
compiler option when the ENABLE_STACK_PROTECTOR build option is
set to "none" (the default).

T

Disable stack protection explicitly

Explicitly disable stack protection via the "-fno-stack-protector"
compiler option when the ENABLE_STACK_PROTECTOR build option is
set to "none" (the default).

This allows the build to complete without link errors on systems where
stack protection is enabled by default in the compiler.

Change-Id: I0a676aa672815235894fb2cd05fa2b196fabb972
Signed-off-by: Simon South <simon@simonsouth.net>

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xlat_table_v2: Fix enable WARMBOOT_ENABLE_DCACHE_EARLY config

The WARMBOOT_ENABLE_DCACHE_EARLY allows caches to be turned on early during
the boot. But the xlat_change_mem_attributes_ctx() API did n

xlat_table_v2: Fix enable WARMBOOT_ENABLE_DCACHE_EARLY config

The WARMBOOT_ENABLE_DCACHE_EARLY allows caches to be turned on early during
the boot. But the xlat_change_mem_attributes_ctx() API did not do the required
cache maintenance after the mmap tables are modified if
WARMBOOT_ENABLE_DCACHE_EARLY is enabled. This meant that when the caches are turned
off during power down, the tables in memory are accessed as part of cache
maintenance for power down, and the tables are not correct at this point which
results in a data abort.
This patch removes the optimization within xlat_change_mem_attributes_ctx()
when WARMBOOT_ENABLE_DCACHE_EARLY is enabled.

Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
Change-Id: I82de3decba87dd13e9856b5f3620a1c8571c8d87

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