History log of /rk3399_ARM-atf/ (Results 12401 – 12425 of 18314)
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382ddb3d20-Sep-2019 Kever Yang <kever.yang@rock-chips.com>

rockchip: Fix typo for TF content text

The 'txet' should be 'text'.

Change-Id: I2217a1adf50c3b86f3087b83c77d9291b280627c
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

6a7cbfd518-Sep-2019 Sandrine Bailleux <sandrine.bailleux@arm.com>

Merge "amlogic: scpi: Add support to retrieve chip ID" into integration

3ea2cc0018-Sep-2019 Sandrine Bailleux <sandrine.bailleux@arm.com>

Merge changes I93ecff4d,I30dd9a95,I8207eea9,Id4197b07,Ib810125b, ... into integration

* changes:
mediatek: mt8183: add MTK MCDI driver
mediatek: mt8183: add MTK SSPM driver
mediatek: mt8183: a

Merge changes I93ecff4d,I30dd9a95,I8207eea9,Id4197b07,Ib810125b, ... into integration

* changes:
mediatek: mt8183: add MTK MCDI driver
mediatek: mt8183: add MTK SSPM driver
mediatek: mt8183: add MTK SPM driver
mediatek: mt8183: add MTK uart driver for controlling clock gate
mediatek: mt8183: configure MCUSYS DCM
mediatek: mt8173: refactor RTC and PMIC drivers

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ea73564318-Sep-2019 Sandrine Bailleux <sandrine.bailleux@arm.com>

Merge changes from topic "db/unsigned_long" into integration

* changes:
Unsigned long should not be used as per coding guidelines
SCTLR and ACTLR are 32-bit for AArch32 and 64-bit for AArch64

5f2849b618-Sep-2019 Sandrine Bailleux <sandrine.bailleux@arm.com>

Merge changes from topic "qemu_sbsa" into integration

* changes:
qemu: Simplify the image size calculation
qemu: introducing sub-platforms to qemu platform

9a006ad117-May-2018 Radoslaw Biernacki <radoslaw.biernacki@linaro.org>

qemu: Simplify the image size calculation

Patch introduce the macro NS_IMAGE_MAX_SIZE to simplify the image size
calculation. Use of additional parenthesis removes the possibility of
improper calcul

qemu: Simplify the image size calculation

Patch introduce the macro NS_IMAGE_MAX_SIZE to simplify the image size
calculation. Use of additional parenthesis removes the possibility of
improper calculations due nested macro expansion for subtraction.
In case of platforms with DRAM window over 32bits, patch also removes
potential problems with type casting, as meminfo.image_size is uint32_t
but macro calculations were done in 64bit space.

Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Change-Id: I2d05a2d9dd6000dba6114df53262995cf85af018

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301d27d917-May-2018 Radoslaw Biernacki <radoslaw.biernacki@linaro.org>

qemu: introducing sub-platforms to qemu platform

This commit change the plat/qemu directory structure into:

`-- plat
`-- qemu
|-- common (files shared with all qemu subplatforms)

qemu: introducing sub-platforms to qemu platform

This commit change the plat/qemu directory structure into:

`-- plat
`-- qemu
|-- common (files shared with all qemu subplatforms)
|-- qemu (original qemu platform)
|-- qemu_sbsa (new sqemu_sbsa platform)
|-- subplat1
`-- subplat2

This opens the possibility of adding new qemu sub-platforms which reuse
existing common platform code. The first platform which will leverage new
structure will be SBSA platform.

Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: Id0d8133e1fffc1b574b69aa2770ebc02bb837a9b

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deb330cb14-Sep-2019 Haojian Zhuang <haojian.zhuang@linaro.org>

hikey: fix to load FIP by partition table.

Avoid to load FIP by hacking address. Load it by partition table instead.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Change-Id: I0283fc2e6e

hikey: fix to load FIP by partition table.

Avoid to load FIP by hacking address. Load it by partition table instead.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Change-Id: I0283fc2e6e459bff14de19d92db4158e05106ee4

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c61cf58f14-Sep-2019 Haojian Zhuang <haojian.zhuang@linaro.org>

hikey960: fix to load FIP by partition table

Avoid to load FIP by hacking address. Load it by partition table instead.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Change-Id: Ib476d024

hikey960: fix to load FIP by partition table

Avoid to load FIP by hacking address. Load it by partition table instead.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Change-Id: Ib476d024a51e4b9705441a0007d78f9fdf0ca078

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f8631f5114-Sep-2019 Haojian Zhuang <haojian.zhuang@linaro.org>

drivers: partition: support different block size

The block size of some storage device is 4096-byte long, such as UFS. But
PARTITION_BLOCK_SIZE is defined as 512-byte long. So replace it by
PLAT_PAR

drivers: partition: support different block size

The block size of some storage device is 4096-byte long, such as UFS. But
PARTITION_BLOCK_SIZE is defined as 512-byte long. So replace it by
PLAT_PARTITION_BLOCK_SIZE. Make it configurable in platform.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Change-Id: Iada05f7c646d0a0f2c0d3b8545540b3cb7153de3

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edcadeb718-Sep-2019 Carlo Caione <ccaione@baylibre.com>

amlogic: makefile: Use PLAT variable when possible

To address the file names.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ib79b8dfa032a1db012c5031d47de61e1a16b5f9a

26d9439318-Sep-2019 Carlo Caione <ccaione@baylibre.com>

amlogic: sha_dma: Move register mappings to platform header

The registers location for the SHA DMA driver is not unique for the
different platforms. Move the mapping out of the driver and into the
p

amlogic: sha_dma: Move register mappings to platform header

The registers location for the SHA DMA driver is not unique for the
different platforms. Move the mapping out of the driver and into the
platform-specific header.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ice64637844a3cb384b01e466cb8c1cea5f764129

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5cfdfc3c16-Sep-2019 Carlo Caione <ccaione@baylibre.com>

amlogic: scpi: Add support to retrieve chip ID

Both kernel and U-Boot use a SMC call to the secure monitor to get the
chip ID. This call is translated by BL31 to a call to the SCP to
retrieve the ID

amlogic: scpi: Add support to retrieve chip ID

Both kernel and U-Boot use a SMC call to the secure monitor to get the
chip ID. This call is translated by BL31 to a call to the SCP to
retrieve the ID. Add a new SiP call and the backing SCPI command.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ib128f5645ee92866e7ebbcd550dacd33f573524b

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ed01e0c416-Sep-2019 Sandrine Bailleux <sandrine.bailleux@arm.com>

Merge changes from topic "raspberry-pi-4-support" into integration

* changes:
rpi3: Do prescaler and control setup in C
rpi3: Prepare for supporting a GIC (in RPi4)
rpi3: Make SHARED_RAM optio

Merge changes from topic "raspberry-pi-4-support" into integration

* changes:
rpi3: Do prescaler and control setup in C
rpi3: Prepare for supporting a GIC (in RPi4)
rpi3: Make SHARED_RAM optional
rpi3: Rename RPI3_IO_BASE to RPI_IO_BASE
rpi3: Move shared rpi3 files into common directory

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f65423cd16-Sep-2019 Sandrine Bailleux <sandrine.bailleux@arm.com>

Merge changes from topic "raspberry-pi-4-support" into integration

* changes:
Add fdt_add_reserved_memory() helper function
qemu: Move and generalise FDT PSCI fixup

c011d7d516-Sep-2019 Sandrine Bailleux <sandrine.bailleux@arm.com>

Merge changes from topic "raspberry-pi-4-support" into integration

* changes:
rpi3: Move rng driver to drivers
rpi3: Move VC mailbox driver into generic drivers directory
rpi3: Move rpi3_hw.h

Merge changes from topic "raspberry-pi-4-support" into integration

* changes:
rpi3: Move rng driver to drivers
rpi3: Move VC mailbox driver into generic drivers directory
rpi3: Move rpi3_hw.h header file to include/rpi_hw.h

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b7ef641d16-Sep-2019 Sandrine Bailleux <sandrine.bailleux@arm.com>

Merge "rpi3: Add "rpi" platform directory" into integration

539061b821-Aug-2019 kenny liang <kenny.liang@mediatek.com>

mediatek: mt8183: add MTK MCDI driver

Add MCDI driver for power saving.

Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I93ecff4d7581f678be09dd8fb5dfaaccd5f2c22c

9fc34bbd21-Aug-2019 kenny liang <kenny.liang@mediatek.com>

mediatek: mt8183: add MTK SSPM driver

Add MTK SSPM driver.

Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I30dd9a95456b8c3c8d18fd22120824eec97634ee

3c25ba4421-Aug-2019 kenny liang <kenny.liang@mediatek.com>

mediatek: mt8183: add MTK SPM driver

Add MTK SPM driver for suspend/resume scenario.

Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I8207eea95914da9e63c62f3afc8329f3ccd9a22c

f9f84f4420-Aug-2019 kenny liang <kenny.liang@mediatek.com>

mediatek: mt8183: add MTK uart driver for controlling clock gate

Add uart clock gate contol for suspend/resume scenario.

Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: Id4197b0720

mediatek: mt8183: add MTK uart driver for controlling clock gate

Add uart clock gate contol for suspend/resume scenario.

Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: Id4197b0720630ec6c74aec206a9b206511bf515a

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e419574e21-Aug-2019 kenny liang <kenny.liang@mediatek.com>

mediatek: mt8183: configure MCUSYS DCM

Configure MCUSYS DCM.

Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: Ib810125b514cbcc43c770377bc71a29a05a19320

f389d0e902-May-2019 kenny liang <kenny.liang@mediatek.com>

mediatek: mt8173: refactor RTC and PMIC drivers

Refactor RTC and PMIC drivers.

Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I74fca536cd61e00c962f080f1ba3759287682ecf

ee006a7903-Sep-2019 Deepika Bhavnani <deepika.bhavnani@arm.com>

Unsigned long should not be used as per coding guidelines

We should either change them to `unsigned int` or `unsigned long long`
when the size of the variable is the same in AArch64 and AArch32 or
t

Unsigned long should not be used as per coding guidelines

We should either change them to `unsigned int` or `unsigned long long`
when the size of the variable is the same in AArch64 and AArch32 or
to `u_register_t` if it is supposed to be 32 bit wide in AArch32
and 64 bit wide in AArch64.

Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I80e2a6edb33248ee88be395829abbd4c36c89abe

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eeb5a7b503-Sep-2019 Deepika Bhavnani <deepika.bhavnani@arm.com>

SCTLR and ACTLR are 32-bit for AArch32 and 64-bit for AArch64

AArch64 System register SCTLR_EL1[31:0] is architecturally mapped
to AArch32 System register SCTLR[31:0]
AArch64 System register ACTLR_E

SCTLR and ACTLR are 32-bit for AArch32 and 64-bit for AArch64

AArch64 System register SCTLR_EL1[31:0] is architecturally mapped
to AArch32 System register SCTLR[31:0]
AArch64 System register ACTLR_EL1[31:0] is architecturally mapped
to AArch32 System register ACTLR[31:0].

`u_register_t` should be used when it's important to store the
contents of a register in its native size

Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I0055422f8cc0454405e011f53c1c4ddcaceb5779

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