1/* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <lib/xlat_tables/xlat_tables_defs.h> 10 11OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 12OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 13ENTRY(bl2_entrypoint) 14 15MEMORY { 16#if BL2_IN_XIP_MEM 17 ROM (rx): ORIGIN = BL2_RO_BASE, LENGTH = BL2_RO_LIMIT - BL2_RO_BASE 18 RAM (rwx): ORIGIN = BL2_RW_BASE, LENGTH = BL2_RW_LIMIT - BL2_RW_BASE 19#else 20 RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE 21#endif 22} 23 24#if !BL2_IN_XIP_MEM 25#define ROM RAM 26#endif 27 28SECTIONS 29{ 30#if BL2_IN_XIP_MEM 31 . = BL2_RO_BASE; 32 ASSERT(. == ALIGN(PAGE_SIZE), 33 "BL2_RO_BASE address is not aligned on a page boundary.") 34#else 35 . = BL2_BASE; 36 ASSERT(. == ALIGN(PAGE_SIZE), 37 "BL2_BASE address is not aligned on a page boundary.") 38#endif 39 40#if SEPARATE_CODE_AND_RODATA 41 .text . : { 42 __TEXT_START__ = .; 43 __TEXT_RESIDENT_START__ = .; 44 *bl2_el3_entrypoint.o(.text*) 45 *(.text.asm.*) 46 __TEXT_RESIDENT_END__ = .; 47 *(SORT_BY_ALIGNMENT(.text*)) 48 *(.vectors) 49 . = ALIGN(PAGE_SIZE); 50 __TEXT_END__ = .; 51 } >ROM 52 53 .rodata . : { 54 __RODATA_START__ = .; 55 *(SORT_BY_ALIGNMENT(.rodata*)) 56 57 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 58 . = ALIGN(8); 59 __PARSER_LIB_DESCS_START__ = .; 60 KEEP(*(.img_parser_lib_descs)) 61 __PARSER_LIB_DESCS_END__ = .; 62 63 /* 64 * Ensure 8-byte alignment for cpu_ops so that its fields are also 65 * aligned. Also ensure cpu_ops inclusion. 66 */ 67 . = ALIGN(8); 68 __CPU_OPS_START__ = .; 69 KEEP(*(cpu_ops)) 70 __CPU_OPS_END__ = .; 71 72 . = ALIGN(PAGE_SIZE); 73 __RODATA_END__ = .; 74 } >ROM 75 76 ASSERT(__TEXT_RESIDENT_END__ - __TEXT_RESIDENT_START__ <= PAGE_SIZE, 77 "Resident part of BL2 has exceeded its limit.") 78#else 79 ro . : { 80 __RO_START__ = .; 81 __TEXT_RESIDENT_START__ = .; 82 *bl2_el3_entrypoint.o(.text*) 83 *(.text.asm.*) 84 __TEXT_RESIDENT_END__ = .; 85 *(SORT_BY_ALIGNMENT(.text*)) 86 *(SORT_BY_ALIGNMENT(.rodata*)) 87 88 /* 89 * Ensure 8-byte alignment for cpu_ops so that its fields are also 90 * aligned. Also ensure cpu_ops inclusion. 91 */ 92 . = ALIGN(8); 93 __CPU_OPS_START__ = .; 94 KEEP(*(cpu_ops)) 95 __CPU_OPS_END__ = .; 96 97 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 98 . = ALIGN(8); 99 __PARSER_LIB_DESCS_START__ = .; 100 KEEP(*(.img_parser_lib_descs)) 101 __PARSER_LIB_DESCS_END__ = .; 102 103 *(.vectors) 104 __RO_END_UNALIGNED__ = .; 105 /* 106 * Memory page(s) mapped to this section will be marked as 107 * read-only, executable. No RW data from the next section must 108 * creep in. Ensure the rest of the current memory page is unused. 109 */ 110 . = ALIGN(PAGE_SIZE); 111 112 __RO_END__ = .; 113 } >ROM 114#endif 115 116 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 117 "cpu_ops not defined for this platform.") 118 119#if BL2_IN_XIP_MEM 120 . = BL2_RW_BASE; 121 ASSERT(BL2_RW_BASE == ALIGN(PAGE_SIZE), 122 "BL2_RW_BASE address is not aligned on a page boundary.") 123#endif 124 125 /* 126 * Define a linker symbol to mark start of the RW memory area for this 127 * image. 128 */ 129 __RW_START__ = . ; 130 131 /* 132 * .data must be placed at a lower address than the stacks if the stack 133 * protector is enabled. Alternatively, the .data.stack_protector_canary 134 * section can be placed independently of the main .data section. 135 */ 136 .data . : { 137 __DATA_RAM_START__ = .; 138 *(SORT_BY_ALIGNMENT(.data*)) 139 __DATA_RAM_END__ = .; 140 } >RAM AT>ROM 141 142 stacks (NOLOAD) : { 143 __STACKS_START__ = .; 144 *(tzfw_normal_stacks) 145 __STACKS_END__ = .; 146 } >RAM 147 148 /* 149 * The .bss section gets initialised to 0 at runtime. 150 * Its base address should be 16-byte aligned for better performance of the 151 * zero-initialization code. 152 */ 153 .bss : ALIGN(16) { 154 __BSS_START__ = .; 155 *(SORT_BY_ALIGNMENT(.bss*)) 156 *(COMMON) 157 __BSS_END__ = .; 158 } >RAM 159 160 /* 161 * The xlat_table section is for full, aligned page tables (4K). 162 * Removing them from .bss avoids forcing 4K alignment on 163 * the .bss section. The tables are initialized to zero by the translation 164 * tables library. 165 */ 166 xlat_table (NOLOAD) : { 167 *(xlat_table) 168 } >RAM 169 170#if USE_COHERENT_MEM 171 /* 172 * The base address of the coherent memory section must be page-aligned (4K) 173 * to guarantee that the coherent data are stored on their own pages and 174 * are not mixed with normal data. This is required to set up the correct 175 * memory attributes for the coherent data page tables. 176 */ 177 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 178 __COHERENT_RAM_START__ = .; 179 *(tzfw_coherent_mem) 180 __COHERENT_RAM_END_UNALIGNED__ = .; 181 /* 182 * Memory page(s) mapped to this section will be marked 183 * as device memory. No other unexpected data must creep in. 184 * Ensure the rest of the current memory page is unused. 185 */ 186 . = ALIGN(PAGE_SIZE); 187 __COHERENT_RAM_END__ = .; 188 } >RAM 189#endif 190 191 /* 192 * Define a linker symbol to mark end of the RW memory area for this 193 * image. 194 */ 195 __RW_END__ = .; 196 __BL2_END__ = .; 197 198#if BL2_IN_XIP_MEM 199 __BL2_RAM_START__ = ADDR(.data); 200 __BL2_RAM_END__ = .; 201 202 __DATA_ROM_START__ = LOADADDR(.data); 203 __DATA_SIZE__ = SIZEOF(.data); 204 205 /* 206 * The .data section is the last PROGBITS section so its end marks the end 207 * of BL2's RO content in XIP memory.. 208 */ 209 __BL2_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__; 210 ASSERT(__BL2_ROM_END__ <= BL2_RO_LIMIT, 211 "BL2's RO content has exceeded its limit.") 212#endif 213 __BSS_SIZE__ = SIZEOF(.bss); 214 215 216#if USE_COHERENT_MEM 217 __COHERENT_RAM_UNALIGNED_SIZE__ = 218 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 219#endif 220 221#if BL2_IN_XIP_MEM 222 ASSERT(. <= BL2_RW_LIMIT, "BL2's RW content has exceeded its limit.") 223#else 224 ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.") 225#endif 226} 227