Merge "Explicitly disable the SPME bit in MDCR_EL3" into integration

Merge "Neoverse N1 Errata Workaround 1542419" into integration

Merge "Fix the CAS spinlock implementation" into integration

Explicitly disable the SPME bit in MDCR_EL3

Currently the MDCR_EL3 initialisation implicitly disables
MDCR_EL3.SPME by using mov_imm.

This patch makes the SPME bit more visible by explicitly
disabl

Explicitly disable the SPME bit in MDCR_EL3

Currently the MDCR_EL3 initialisation implicitly disables
MDCR_EL3.SPME by using mov_imm.

This patch makes the SPME bit more visible by explicitly
disabling it and documenting its use in different versions
of the architecture.

Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com>
Change-Id: I221fdf314f01622f46ac5aa43388f59fa17a29b3

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Neoverse N1 Errata Workaround 1542419

Coherent I-cache is causing a prefetch violation where when the core
executes an instruction that has recently been modified, the core might
fetch a stale instr

Neoverse N1 Errata Workaround 1542419

Coherent I-cache is causing a prefetch violation where when the core
executes an instruction that has recently been modified, the core might
fetch a stale instruction which violates the ordering of instruction
fetches.

The workaround includes an instruction sequence to implementation
defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap
handler to execute a TLB inner-shareable invalidation to an arbitrary
address followed by a DSB.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6

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Merge "delay: timeout detection support" into integration

Fix the CAS spinlock implementation

Make the spinlock implementation use ARMv8.1-LSE CAS instruction based
on a platform build option. The CAS-based implementation used to be
unconditionally selecte

Fix the CAS spinlock implementation

Make the spinlock implementation use ARMv8.1-LSE CAS instruction based
on a platform build option. The CAS-based implementation used to be
unconditionally selected for all ARM8.1+ platforms.

The previous CAS spinlock implementation had a bug wherein the spin_unlock()
implementation had an `sev` after `stlr` which is not sufficient. A dsb is
needed to ensure that the stlr completes prior to the sev. Having a dsb is
heavyweight and a better solution would be to use load exclusive semantics
to monitor the lock and wake up from wfe when a store happens to the lock.
The patch implements the same.

Change-Id: I5283ce4a889376e4cc01d1b9d09afa8229a2e522
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>

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delay: timeout detection support

Introduce timeout_init_us/timeout_elapsed() delay tracking with CNTPCT.

timeout_init_us(some_timeout_us); returns a reference to detect
timeout for the provided mic

delay: timeout detection support

Introduce timeout_init_us/timeout_elapsed() delay tracking with CNTPCT.

timeout_init_us(some_timeout_us); returns a reference to detect
timeout for the provided microsecond delay value from current time.

timeout_elapsed(reference) return true/false whether the reference
timeout is elapsed.

Cherry picked from OP-TEE implementation [1].
[1] commit 33d30a74502b ("core: timeout detection support")

Minor:
- Remove stm32mp platform duplicated implementation.
- Add new include in marvell ble.mk

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: Iaef6d43c11a2e6992fb48efdc674a0552755ad9c

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Merge "TF-A: Add support for ARMv8.3-PAuth in BL1 SMC calls and BL2U" into integration

TF-A: Add support for ARMv8.3-PAuth in BL1 SMC calls and BL2U

This patch adds support for ARMv8.3-PAuth in BL1 SMC calls and
BL2U image for firmware updates by programming APIAKey_EL1 registers
and

TF-A: Add support for ARMv8.3-PAuth in BL1 SMC calls and BL2U

This patch adds support for ARMv8.3-PAuth in BL1 SMC calls and
BL2U image for firmware updates by programming APIAKey_EL1 registers
and enabling Pointer Authentication in EL3 and EL1 respectively.

Change-Id: I875d952aba8242caf74fb5f4f2d2af6f0c768c08
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

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Merge "Introducing support for Cortex-A65AE" into integration

Introducing support for Cortex-A65AE

Change-Id: I1ea2bf088f1e001cdbd377cbfb7c6a2866af0422
Signed-off-by: Imre Kis <imre.kis@arm.com>

Merge changes from topic "stm32mp_corrections_w40" into integration

* changes:
gpio: stm32_gpio: do not mix error code types
fdts: stm32mp1: move FDCAN to PLL4_R
mmc: increase delay between AC

Merge changes from topic "stm32mp_corrections_w40" into integration

* changes:
gpio: stm32_gpio: do not mix error code types
fdts: stm32mp1: move FDCAN to PLL4_R
mmc: increase delay between ACMD41 retries
crypto: stm32_hash: align stm32_hash_update() prototype

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Merge "Add missing support for BL2_AT_EL3 in XIP memory" into integration

Merge changes from topic "qemu_sbsa" into integration

* changes:
qemu/qemu_sbsa: Adding memory mapping for both FLASH0/FLASH1
qemu/qemu_sbsa: Adding Qemu SBSA platform

Merge changes I0355e084,I6a6dd1c0 into integration

* changes:
mediatek: mt8183: add EMI MPU driver for DRAM protection
mediatek: mt8183: add DEVAPC driver to control protection

Merge "a5ds: Add handler for when user tries to switch off secondary cores" into integration

gpio: stm32_gpio: do not mix error code types

Change-Id: I84f8a99be2dcdf7c51fbecdb324df8e2f32cc855
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier

gpio: stm32_gpio: do not mix error code types

Change-Id: I84f8a99be2dcdf7c51fbecdb324df8e2f32cc855
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fdts: stm32mp1: move FDCAN to PLL4_R

LTDC modifies the clock frequency to adapt it to the display. Such
frequency change is not detected by the FDCAN driver that instead
caches the value at probe an

fdts: stm32mp1: move FDCAN to PLL4_R

LTDC modifies the clock frequency to adapt it to the display. Such
frequency change is not detected by the FDCAN driver that instead
caches the value at probe and pretends to use it later.

This change fixes the issue by moving the FDCAN to PLL4_R,
leaving the LTDC alone on PLL4_Q.

Signed-off-by: Antonio Borneo <antonio.borneo@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I8230868b2b5fd6deb6e3f9dc3911030d8d484c58

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mmc: increase delay between ACMD41 retries

In the SD Specification, Power Up Diagram of Card figure, the Timeout
value for initialization process (ACMD41 command retries) is 1 second.
Align to match

mmc: increase delay between ACMD41 retries

In the SD Specification, Power Up Diagram of Card figure, the Timeout
value for initialization process (ACMD41 command retries) is 1 second.
Align to match MMC cards (in mmc_send_op_cond()) and Linux kernel code,
and set the delay between ACMD41 command retries to 10ms.

Change-Id: I2e07cb9944e7d7b72f2d4b13e0505e6751458091
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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crypto: stm32_hash: align stm32_hash_update() prototype

Use size_t for length parameter in header file, as in .c file.

Change-Id: I310f2a6159cde1c069b4f814f6558c2488c203ec
Signed-off-by: Yann Gauti

crypto: stm32_hash: align stm32_hash_update() prototype

Use size_t for length parameter in header file, as in .c file.

Change-Id: I310f2a6159cde1c069b4f814f6558c2488c203ec
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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a5ds: Add handler for when user tries to switch off secondary cores

a5ds only has always-on power domain and there is no power control
present. However, without the pwr_domain_off handler, the kerne

a5ds: Add handler for when user tries to switch off secondary cores

a5ds only has always-on power domain and there is no power control
present. However, without the pwr_domain_off handler, the kernel
panics when the user will try to switch off secondary cores. The
a5ds_pwr_domain_off handler will prevent kernel from crashing,
i.e. the kernel will attempt but fail to shut down the secondary CPUs
if the user tries to switch them offline.

Change-Id: I3c2239a1b6f035113ddbdda063c8495000cbe30c
Signed-off-by: Usama Arif <usama.arif@arm.com>

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mediatek: mt8183: add EMI MPU driver for DRAM protection

Add EMI MPU driver for DRAM protection.

Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I0355e084184b5396ad8ac99fff6ef9d050

mediatek: mt8183: add EMI MPU driver for DRAM protection

Add EMI MPU driver for DRAM protection.

Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I0355e084184b5396ad8ac99fff6ef9d050fb5e96

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mediatek: mt8183: add DEVAPC driver to control protection

Add DEVAPC driver to control protection.

Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I6a6dd1c0bffa372b6df2cb604ca5e02e

mediatek: mt8183: add DEVAPC driver to control protection

Add DEVAPC driver to control protection.

Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I6a6dd1c0bffa372b6df2cb604ca5e02eabbb9d26

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Merge "Introducing support for Cortex-A65" into integration