Tegra194: memctrl: force seswr/rd transactions as passsthru & coherent

Force memory transactions from seswr and sesrd as coherent_snoop from
no-override. This is necessary as niso clients should use

Tegra194: memctrl: force seswr/rd transactions as passsthru & coherent

Force memory transactions from seswr and sesrd as coherent_snoop from
no-override. This is necessary as niso clients should use coherent
path.

Presently its set as FORCE_COHERENT_SNOOP. Once SE+TZ is enabled
with SMMU, this needs to be replaced by FORCE_COHERENT.

Change-Id: I8b50722de743b9028129b4715769ef93deab73b5
Signed-off-by: Puneet Saxena <puneets@nvidia.com>

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Tegra194: Request CG7 from last core in cluster

- SC7 requires all the cluster groups to be in CG7 state, else
is_sc7_allowed will get denied
- As a WAR while requesting CC6, request CG7 as well
-

Tegra194: Request CG7 from last core in cluster

- SC7 requires all the cluster groups to be in CG7 state, else
is_sc7_allowed will get denied
- As a WAR while requesting CC6, request CG7 as well
- CG7 request will not be honored if it is not last core in Cluster
group
- This is just to satisfy MCE for now as CG7 is going to be defeatured

Change-Id: Ibf2f8a365a2e46bd427abd563da772b6b618350f
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>

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Tegra194: toggle SE clock during context save/restore

This patch adds support to toggle SE clock, using the bpmp_ipc
interface, to enable SE context save/restore. The SE sequence mostly
gets called

Tegra194: toggle SE clock during context save/restore

This patch adds support to toggle SE clock, using the bpmp_ipc
interface, to enable SE context save/restore. The SE sequence mostly
gets called during System Suspend/Resume.

Change-Id: I9cee12a9e14861d5e3c8c4f18b4d7f898b6ebfa7
Signed-off-by: steven kao <skao@nvidia.com>

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Tegra: bpmp: fix header file paths

This patch fixes the header file paths to include debug.h
from the right location.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: If303792d2169158f

Tegra: bpmp: fix header file paths

This patch fixes the header file paths to include debug.h
from the right location.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: If303792d2169158f436ae6aa5b6d7a4f88e28f7b

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Merge "Revert "Changes necessary to support SEPARATE_NOBITS_REGION feature"" into integration

Merge "Revert "plat/arm: Add support for SEPARATE_NOBITS_REGION"" into integration

Revert "plat/arm: Add support for SEPARATE_NOBITS_REGION"

This reverts commit d433bbdd459c222e5bf5ca87319807465b246d8c.

Change-Id: I46c69dce704a1ce1b50452dd4d62425c4a67f7f0

Merge "Errata workarounds N1 1043202, 1315703 default off" into integration

Errata workarounds N1 1043202, 1315703 default off

Setting errata workarounds for N1 1043202 and 1315703 to 0 since
they should be turned off by default.

Signed-off-by: Lauren Wehrmeister <lauren.w

Errata workarounds N1 1043202, 1315703 default off

Setting errata workarounds for N1 1043202 and 1315703 to 0 since
they should be turned off by default.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I116673a4ddcf64436e90d70133f035a133989ed9

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qemu: Implement qemu_system_off via semihosting.

This makes the PSCI SYSTEM_OFF call work on QEMU. It assumes that QEMU has
semihosting enabled, but that is already assumed by the image loader.

Sig

qemu: Implement qemu_system_off via semihosting.

This makes the PSCI SYSTEM_OFF call work on QEMU. It assumes that QEMU has
semihosting enabled, but that is already assumed by the image loader.

Signed-off-by: Andrew Walbran <qwandor@google.com>
Change-Id: I0fb7cf7909262b675c3143efeac07f4d60730b03

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qemu: Support ARM_LINUX_KERNEL_AS_BL33 to pass FDT address.

This lets the Linux kernel or any other image which expects an FDT in x0 be
loaded directly as BL33 without a separate bootloader on QEMU.

qemu: Support ARM_LINUX_KERNEL_AS_BL33 to pass FDT address.

This lets the Linux kernel or any other image which expects an FDT in x0 be
loaded directly as BL33 without a separate bootloader on QEMU.

Signed-off-by: Andrew Walbran <qwandor@google.com>
Change-Id: Ia8eb4710a3d97cdd877af3b8aae36a2de7cfc654

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Merge "spm-mm: correcting instructions to build SPM for FVP" into integration

spm-mm: correcting instructions to build SPM for FVP

Out of two possible implementation of Secure Partition Manager(SPM)
currently only Management mode (MM) design is supported and the support
for S

spm-mm: correcting instructions to build SPM for FVP

Out of two possible implementation of Secure Partition Manager(SPM)
currently only Management mode (MM) design is supported and the support
for SPM based on SPCI Alpha 1 prototype has been removed.

Earlier both implementation used common build flag "ENABLE_SPM" but it
has since been decoupled and MM uses a separate build FLAG "SPM_MM".

Instructions to build it for FVP was still using "ENABLE_SPM", which has
beend corrected in this patch.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I505b98173d6051816436aa602ced6dbec4efc776

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xilinx: versal: PLM to ATF handover

Parse the parameter structure the PLM populates, to populate the
bl32 and bl33 image structures.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xili

xilinx: versal: PLM to ATF handover

Parse the parameter structure the PLM populates, to populate the
bl32 and bl33 image structures.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I317072d1086f6cc6f90883c1b8b6d086ff57b443

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xilinx: common: Move ATF handover to common file

ATF handover can be used by Xilinx platforms, so move it to common
file from platform specific files.

Signed-off-by: Venkatesh Yadav Abbarapu <venka

xilinx: common: Move ATF handover to common file

ATF handover can be used by Xilinx platforms, so move it to common
file from platform specific files.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I5f0839351f534619de581d1953c8427a079487e0

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Revert "Changes necessary to support SEPARATE_NOBITS_REGION feature"

This reverts commit 76d84cbc60ab3ee7bf40d53487f85ed7417bdcc3.

Change-Id: I867af7af3d9f5e568101f79b9ebea578e5cb2a4b

Merge "plat/arm: Add support for SEPARATE_NOBITS_REGION" into integration

Merge "Changes necessary to support SEPARATE_NOBITS_REGION feature" into integration

Prevent speculative execution past ERET

Even though ERET always causes a jump to another address, aarch64 CPUs
speculatively execute following instructions as if the ERET
instruction was not a jump

Prevent speculative execution past ERET

Even though ERET always causes a jump to another address, aarch64 CPUs
speculatively execute following instructions as if the ERET
instruction was not a jump instruction.
The speculative execution does not cross privilege-levels (to the jump
target as one would expect), but it continues on the kernel privilege
level as if the ERET instruction did not change the control flow -
thus execution anything that is accidentally linked after the ERET
instruction. Later, the results of this speculative execution are
always architecturally discarded, however they can leak data using
microarchitectural side channels. This speculative execution is very
reliable (seems to be unconditional) and it manages to complete even
relatively performance-heavy operations (e.g. multiple dependent
fetches from uncached memory).

This was fixed in Linux, FreeBSD, OpenBSD and Optee OS:
https://github.com/torvalds/linux/commit/679db70801da9fda91d26caf13bf5b5ccc74e8e8
https://github.com/freebsd/freebsd/commit/29fb48ace4186a41c409fde52bcf4216e9e50b61
https://github.com/openbsd/src/commit/3a08873ece1cb28ace89fd65e8f3c1375cc98de2
https://github.com/OP-TEE/optee_os/commit/abfd092aa19f9c0251e3d5551e2d68a9ebcfec8a

It is demonstrated in a SafeSide example:
https://github.com/google/safeside/blob/master/demos/eret_hvc_smc_wrapper.cc
https://github.com/google/safeside/blob/master/kernel_modules/kmod_eret_hvc_smc/eret_hvc_smc_module.c

Signed-off-by: Anthony Steinhauser <asteinhauser@google.com>
Change-Id: Iead39b0b9fb4b8d8b5609daaa8be81497ba63a0f

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Ignore the ctags file

Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: Ic78bda00aba0e350095c3dcd59f688f4a27ed1d4

Merge "FDT helper functions: Fix MISRA issues" into integration

Merge changes from topic "add-versal-soc-support" into integration

* changes:
plat: xilinx: Move pm_client.h to common directory
plat: xilinx: versal: Make silicon default build target
xilinx:

Merge changes from topic "add-versal-soc-support" into integration

* changes:
plat: xilinx: Move pm_client.h to common directory
plat: xilinx: versal: Make silicon default build target
xilinx: versal: Wire silicon default setup
versal: Increase OCM memory size for DEBUG builds
plat: xilinx: versal: Dont set IOU switch clock
arm64: versal: Adjust cpu clock for versal virtual
xilinx: versal: Add support for PM_GET_OPERATING_CHARACTERISTIC EEMI call
plat: versal: Add Get_ChipID API
plat: xilinx: versal: Add load Pdi API support
xilinx: versal: Add feature check API
xilinx: versal: Implement set wakeup source for client
plat: xilinx: versal: Add GET_CALLBACK_DATA function
xilinx: versal: Add PSCI APIs for system shutdown & reset
xilinx: versal: Add PSCI APIs for suspend/resume
xilinx: versal: Remove no_pmc ops to ON power domain
xilinx: versal: Add set wakeup source API
xilinx: versal: Add client wakeup API
xilinx: versal: Add query data API
xilinx: versal: Add request wakeup API
xilinx: versal: Add PM_INIT_FINALIZE API for versal
xilinx: versal: Add support of PM_GET_TRUSTZONE_VERSION API
xilinx: versal: enable ipi mailbox service
xilinx: move ipi mailbox svc to xilinx common
plat: xilinx: versal: Implement PM IOCTL API
xilinx: versal: Implement power down/restart related EEMI API
xilinx: versal: Add SMC handler for EEMI API
xilinx: versal: Implement PLL related PM APIs
xilinx: versal: Implement clock related PM APIs
xilinx: versal: Implement pin control related PM APIs
xilinx: versal: Implement reset related PM APIs
xilinx: versal: Implement device related PM APIs
xilinx: versal: Add support for suspend related APIs
xilinx: versal: Add get_api_version support
xilinx: Add support to send PM API to PMC using IPI for versal
plat: xilinx: versal: Move versal_def.h to include directory
plat: xilinx: versal: Move versal_private.h to include directory
plat: xilinx: zynqmp: Use GIC framework for warm restart

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Xilinx zynqmp: add missing pin control group for ethernet 0.

Signed-off-by: Norbert Werner <opensource@lab-w.org>
Change-Id: I3264515e5901689328861964ff664ff08b6e852c

xlat_tables_v2: simplify end address checks in mmap_add_region_check()

Use end_va and end_pa defined at the beginning of this function.

Change-Id: I0e8b3b35fceb87b5d35397eb892d4fe92ba90b4c
Signed-o

xlat_tables_v2: simplify end address checks in mmap_add_region_check()

Use end_va and end_pa defined at the beginning of this function.

Change-Id: I0e8b3b35fceb87b5d35397eb892d4fe92ba90b4c
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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Merge "Set lld as the default linker for Clang builds" into integration