1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <errno.h> 10 #include <stddef.h> 11 #include <string.h> 12 13 #include <platform_def.h> 14 15 #include <arch.h> 16 #include <arch_helpers.h> 17 #include <bl31/bl31.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <cortex_a53.h> 21 #include <cortex_a57.h> 22 #include <denver.h> 23 #include <drivers/console.h> 24 #include <lib/mmio.h> 25 #include <lib/utils.h> 26 #include <lib/utils_def.h> 27 #include <plat/common/platform.h> 28 29 #include <memctrl.h> 30 #include <profiler.h> 31 #include <tegra_def.h> 32 #include <tegra_platform.h> 33 #include <tegra_private.h> 34 35 /* length of Trusty's input parameters (in bytes) */ 36 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 37 38 extern void memcpy16(void *dest, const void *src, unsigned int length); 39 40 /******************************************************************************* 41 * Declarations of linker defined symbols which will help us find the layout 42 * of trusted SRAM 43 ******************************************************************************/ 44 45 IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START); 46 47 static const uint64_t BL31_RW_END = BL_END; 48 static const uint64_t BL31_RODATA_BASE = BL_RO_DATA_BASE; 49 static const uint64_t BL31_RODATA_END = BL_RO_DATA_END; 50 static const uint64_t TEXT_START = BL_CODE_BASE; 51 static const uint64_t TEXT_END = BL_CODE_END; 52 53 extern uint64_t tegra_bl31_phys_base; 54 55 static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; 56 static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { 57 .tzdram_size = TZDRAM_SIZE 58 }; 59 #ifdef SPD_trusty 60 static aapcs64_params_t bl32_args; 61 #endif 62 63 /******************************************************************************* 64 * This variable holds the non-secure image entry address 65 ******************************************************************************/ 66 extern uint64_t ns_image_entrypoint; 67 68 /******************************************************************************* 69 * Return a pointer to the 'entry_point_info' structure of the next image for 70 * security state specified. BL33 corresponds to the non-secure image type 71 * while BL32 corresponds to the secure image type. 72 ******************************************************************************/ 73 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 74 { 75 entry_point_info_t *ep = NULL; 76 77 /* return BL32 entry point info if it is valid */ 78 if (type == NON_SECURE) { 79 ep = &bl33_image_ep_info; 80 } else if ((type == SECURE) && (bl32_image_ep_info.pc != 0U)) { 81 ep = &bl32_image_ep_info; 82 } 83 84 return ep; 85 } 86 87 /******************************************************************************* 88 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image 89 * passes this platform specific information. 90 ******************************************************************************/ 91 plat_params_from_bl2_t *bl31_get_plat_params(void) 92 { 93 return &plat_bl31_params_from_bl2; 94 } 95 96 /******************************************************************************* 97 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image 98 * info. 99 ******************************************************************************/ 100 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 101 u_register_t arg2, u_register_t arg3) 102 { 103 struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0; 104 plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1; 105 image_info_t bl32_img_info = { {0} }; 106 int32_t ret; 107 108 /* 109 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so 110 * there's no argument to relay from a previous bootloader. Platforms 111 * might use custom ways to get arguments. 112 */ 113 if (arg_from_bl2 == NULL) { 114 arg_from_bl2 = plat_get_bl31_params(); 115 } 116 if (plat_params == NULL) { 117 plat_params = plat_get_bl31_plat_params(); 118 } 119 120 /* 121 * Copy BL3-3, BL3-2 entry point information. 122 * They are stored in Secure RAM, in BL2's address space. 123 */ 124 assert(arg_from_bl2 != NULL); 125 assert(arg_from_bl2->bl33_ep_info != NULL); 126 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info; 127 128 if (arg_from_bl2->bl32_ep_info != NULL) { 129 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info; 130 #ifdef SPD_trusty 131 /* save BL32 boot parameters */ 132 memcpy(&bl32_args, &arg_from_bl2->bl32_ep_info->args, sizeof(bl32_args)); 133 #endif 134 } 135 136 /* 137 * Parse platform specific parameters 138 */ 139 assert(plat_params != NULL); 140 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; 141 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; 142 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id; 143 plat_bl31_params_from_bl2.l2_ecc_parity_prot_dis = plat_params->l2_ecc_parity_prot_dis; 144 plat_bl31_params_from_bl2.sc7entry_fw_size = plat_params->sc7entry_fw_size; 145 plat_bl31_params_from_bl2.sc7entry_fw_base = plat_params->sc7entry_fw_base; 146 147 /* 148 * It is very important that we run either from TZDRAM or TZSRAM base. 149 * Add an explicit check here. 150 */ 151 if ((plat_bl31_params_from_bl2.tzdram_base != (uint64_t)BL31_BASE) && 152 (TEGRA_TZRAM_BASE != BL31_BASE)) { 153 panic(); 154 } 155 156 /* 157 * Enable console for the platform 158 */ 159 plat_enable_console(plat_params->uart_id); 160 161 /* 162 * The previous bootloader passes the base address of the shared memory 163 * location to store the boot profiler logs. Sanity check the 164 * address and initialise the profiler library, if it looks ok. 165 */ 166 ret = bl31_check_ns_address(plat_params->boot_profiler_shmem_base, 167 PROFILER_SIZE_BYTES); 168 if (ret == (int32_t)0) { 169 170 /* store the membase for the profiler lib */ 171 plat_bl31_params_from_bl2.boot_profiler_shmem_base = 172 plat_params->boot_profiler_shmem_base; 173 174 /* initialise the profiler library */ 175 boot_profiler_init(plat_params->boot_profiler_shmem_base, 176 TEGRA_TMRUS_BASE); 177 } 178 179 /* 180 * Add timestamp for platform early setup entry. 181 */ 182 boot_profiler_add_record("[TF] early setup entry"); 183 184 /* 185 * Initialize delay timer 186 */ 187 tegra_delay_timer_init(); 188 189 /* Early platform setup for Tegra SoCs */ 190 plat_early_platform_setup(); 191 192 /* 193 * Do initial security configuration to allow DRAM/device access. 194 */ 195 tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base, 196 (uint32_t)plat_bl31_params_from_bl2.tzdram_size); 197 198 /* 199 * The previous bootloader might not have placed the BL32 image 200 * inside the TZDRAM. We check the BL32 image info to find out 201 * the base/PC values and relocate the image if necessary. 202 */ 203 if (arg_from_bl2->bl32_image_info != NULL) { 204 205 uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end; 206 bl32_img_info = *arg_from_bl2->bl32_image_info; 207 208 /* Relocate BL32 if it resides outside of the TZDRAM */ 209 tzdram_start = plat_bl31_params_from_bl2.tzdram_base; 210 tzdram_end = plat_bl31_params_from_bl2.tzdram_base + 211 plat_bl31_params_from_bl2.tzdram_size; 212 bl32_start = bl32_img_info.image_base; 213 bl32_end = bl32_img_info.image_base + bl32_img_info.image_size; 214 215 assert(tzdram_end > tzdram_start); 216 assert(bl32_end > bl32_start); 217 assert(bl32_image_ep_info.pc > tzdram_start); 218 assert(bl32_image_ep_info.pc < tzdram_end); 219 220 /* relocate BL32 */ 221 if ((bl32_start >= tzdram_end) || (bl32_end <= tzdram_start)) { 222 223 INFO("Relocate BL32 to TZDRAM\n"); 224 225 (void)memcpy16((void *)(uintptr_t)bl32_image_ep_info.pc, 226 (void *)(uintptr_t)bl32_start, 227 bl32_img_info.image_size); 228 229 /* clean up non-secure intermediate buffer */ 230 zeromem((void *)(uintptr_t)bl32_start, 231 bl32_img_info.image_size); 232 } 233 } 234 235 /* 236 * Add timestamp for platform early setup exit. 237 */ 238 boot_profiler_add_record("[TF] early setup exit"); 239 240 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", 241 (((read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK) 242 == DENVER_IMPL) ? "Denver" : "ARM", read_mpidr()); 243 } 244 245 #ifdef SPD_trusty 246 void plat_trusty_set_boot_args(aapcs64_params_t *args) 247 { 248 /* 249 * arg0 = TZDRAM aperture available for BL32 250 * arg1 = BL32 boot params 251 * arg2 = EKS Blob Length 252 * arg3 = Boot Profiler Carveout Base 253 */ 254 args->arg0 = bl32_args.arg0; 255 args->arg1 = bl32_args.arg2; 256 257 /* update EKS size */ 258 args->arg2 = bl32_args.arg4; 259 260 /* Profiler Carveout Base */ 261 args->arg3 = bl32_args.arg5; 262 } 263 #endif 264 265 /******************************************************************************* 266 * Initialize the gic, configure the SCR. 267 ******************************************************************************/ 268 void bl31_platform_setup(void) 269 { 270 /* 271 * Add timestamp for platform setup entry. 272 */ 273 boot_profiler_add_record("[TF] plat setup entry"); 274 275 /* Initialize the gic cpu and distributor interfaces */ 276 plat_gic_setup(); 277 278 /* 279 * Setup secondary CPU POR infrastructure. 280 */ 281 plat_secondary_setup(); 282 283 /* 284 * Initial Memory Controller configuration. 285 */ 286 tegra_memctrl_setup(); 287 288 /* 289 * Set up the TZRAM memory aperture to allow only secure world 290 * access 291 */ 292 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE); 293 294 /* 295 * Late setup handler to allow platforms to performs additional 296 * functionality. 297 * This handler gets called with MMU enabled. 298 */ 299 plat_late_platform_setup(); 300 301 /* 302 * Add timestamp for platform setup exit. 303 */ 304 boot_profiler_add_record("[TF] plat setup exit"); 305 306 INFO("BL3-1: Tegra platform setup complete\n"); 307 } 308 309 /******************************************************************************* 310 * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit 311 ******************************************************************************/ 312 void bl31_plat_runtime_setup(void) 313 { 314 /* 315 * During cold boot, it is observed that the arbitration 316 * bit is set in the Memory controller leading to false 317 * error interrupts in the non-secure world. To avoid 318 * this, clean the interrupt status register before 319 * booting into the non-secure world 320 */ 321 tegra_memctrl_clear_pending_interrupts(); 322 323 /* 324 * During boot, USB3 and flash media (SDMMC/SATA) devices need 325 * access to IRAM. Because these clients connect to the MC and 326 * do not have a direct path to the IRAM, the MC implements AHB 327 * redirection during boot to allow path to IRAM. In this mode 328 * accesses to a programmed memory address aperture are directed 329 * to the AHB bus, allowing access to the IRAM. This mode must be 330 * disabled before we jump to the non-secure world. 331 */ 332 tegra_memctrl_disable_ahb_redirection(); 333 334 /* 335 * Add final timestamp before exiting BL31. 336 */ 337 boot_profiler_add_record("[TF] bl31 exit"); 338 boot_profiler_deinit(); 339 } 340 341 /******************************************************************************* 342 * Perform the very early platform specific architectural setup here. At the 343 * moment this only intializes the mmu in a quick and dirty way. 344 ******************************************************************************/ 345 void bl31_plat_arch_setup(void) 346 { 347 uint64_t rw_start = BL31_RW_START; 348 uint64_t rw_size = BL31_RW_END - BL31_RW_START; 349 uint64_t rodata_start = BL31_RODATA_BASE; 350 uint64_t rodata_size = BL31_RODATA_END - BL31_RODATA_BASE; 351 uint64_t code_base = TEXT_START; 352 uint64_t code_size = TEXT_END - TEXT_START; 353 const mmap_region_t *plat_mmio_map = NULL; 354 #if USE_COHERENT_MEM 355 uint32_t coh_start, coh_size; 356 #endif 357 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 358 359 /* 360 * Add timestamp for arch setup entry. 361 */ 362 boot_profiler_add_record("[TF] arch setup entry"); 363 364 /* add MMIO space */ 365 plat_mmio_map = plat_get_mmio_map(); 366 if (plat_mmio_map != NULL) { 367 mmap_add(plat_mmio_map); 368 } else { 369 WARN("MMIO map not available\n"); 370 } 371 372 /* add memory regions */ 373 mmap_add_region(rw_start, rw_start, 374 rw_size, 375 MT_MEMORY | MT_RW | MT_SECURE); 376 mmap_add_region(rodata_start, rodata_start, 377 rodata_size, 378 MT_RO_DATA | MT_SECURE); 379 mmap_add_region(code_base, code_base, 380 code_size, 381 MT_CODE | MT_SECURE); 382 383 #if USE_COHERENT_MEM 384 coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE); 385 coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE; 386 387 mmap_add_region(coh_start, coh_start, 388 coh_size, 389 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE); 390 #endif 391 392 /* map TZDRAM used by BL31 as coherent memory */ 393 if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) { 394 mmap_add_region(params_from_bl2->tzdram_base, 395 params_from_bl2->tzdram_base, 396 BL31_SIZE, 397 MT_DEVICE | MT_RW | MT_SECURE); 398 } 399 400 /* set up translation tables */ 401 init_xlat_tables(); 402 403 /* enable the MMU */ 404 enable_mmu_el3(0); 405 406 /* 407 * Add timestamp for arch setup exit. 408 */ 409 boot_profiler_add_record("[TF] arch setup exit"); 410 411 INFO("BL3-1: Tegra: MMU enabled\n"); 412 } 413 414 /******************************************************************************* 415 * Check if the given NS DRAM range is valid 416 ******************************************************************************/ 417 int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes) 418 { 419 uint64_t end = base + size_in_bytes - U(1); 420 int32_t ret = 0; 421 422 /* 423 * Check if the NS DRAM address is valid 424 */ 425 if ((base < TEGRA_DRAM_BASE) || (base >= TEGRA_DRAM_END) || 426 (end > TEGRA_DRAM_END)) { 427 428 ERROR("NS address 0x%llx is out-of-bounds!\n", base); 429 ret = -EFAULT; 430 } 431 432 /* 433 * TZDRAM aperture contains the BL31 and BL32 images, so we need 434 * to check if the NS DRAM range overlaps the TZDRAM aperture. 435 */ 436 if ((base < (uint64_t)TZDRAM_END) && (end > tegra_bl31_phys_base)) { 437 ERROR("NS address 0x%llx overlaps TZDRAM!\n", base); 438 ret = -ENOTSUP; 439 } 440 441 /* valid NS address */ 442 return ret; 443 } 444