Merge "CMake buildsystem design document" into integration

CMake buildsystem design document

Change-Id: I9b69f2731b0d43ead4cacfa9844c6137c57f5aec
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

fconf: Add namespace guidance inside documentation

Change-Id: I50707d1836c7f5e4ef162c00256624a1f278baef
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

plat/arm/sgi: mark remote chip shared ram as non-cacheable

Shared RAM region in the remote chip's memory is used as one of the
mailbox region (SCMI payload area) through which the AP core on the
loc

plat/arm/sgi: mark remote chip shared ram as non-cacheable

Shared RAM region in the remote chip's memory is used as one of the
mailbox region (SCMI payload area) through which the AP core on the
local chip and SCP core on the remote chip exchange SCMI protocol
message during the initialization. Mark this region as non-cacheable in
the MMAP entry to prevent local AP core from reading stale data from the
cache.

Change-Id: I7e9dc5fbcc3b40e9bcff5499f15abd2aadaed385
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>

show more ...

n1sdp: Enable the NEOVERSE_N1_EXTERNAL_LLC flag

Since N1SDP has a system level cache which is an
external LLC enable the NEOVERSE_N1_EXTERNAL_LLC flag.

Change-Id: Idb34274e61e7fd9db5485862a0caa497f

n1sdp: Enable the NEOVERSE_N1_EXTERNAL_LLC flag

Since N1SDP has a system level cache which is an
external LLC enable the NEOVERSE_N1_EXTERNAL_LLC flag.

Change-Id: Idb34274e61e7fd9db5485862a0caa497f3e290c7
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

show more ...

Merge changes from topic "stm32mp1-multi-image" into integration

* changes:
stm32mp1: platform.mk: support generating multiple images in one build
stm32mp1: platform.mk: migrate to implicit rule

Merge changes from topic "stm32mp1-multi-image" into integration

* changes:
stm32mp1: platform.mk: support generating multiple images in one build
stm32mp1: platform.mk: migrate to implicit rules
stm32mp1: platform.mk: derive map file name from target name
stm32mp1: platform.mk: generate linker script with fixed name
stm32mp1: platform.mk: use PHONY for the appropriate targets

show more ...

Merge "plat: imx8mm: provide uart base as build option" into integration

Merge "hikey960: Enable system power off callback" into integration

Merge changes from topic "xlat" into integration

* changes:
Factor xlat_table sections in linker scripts out into a header file
xlat_tables_v2: use ARRAY_SIZE in REGISTER_XLAT_CONTEXT_FULL_SPEC

Merge changes from topic "xlat" into integration

* changes:
Factor xlat_table sections in linker scripts out into a header file
xlat_tables_v2: use ARRAY_SIZE in REGISTER_XLAT_CONTEXT_FULL_SPEC
xlat_tables_v2: merge REGISTER_XLAT_CONTEXT_{FULL_SPEC,RO_BASE_TABLE}

show more ...

Changelog: Add dualroot CoT entries

Change-Id: I60df17764b5170be6bc932808e8890fe1bb0b50f
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Merge "plat/arm: Retrieve the right ROTPK when using the dualroot CoT" into integration

Factor xlat_table sections in linker scripts out into a header file

TF-A has so many linker scripts, at least one linker script for each BL
image, and some platforms have their own ones. They duplic

Factor xlat_table sections in linker scripts out into a header file

TF-A has so many linker scripts, at least one linker script for each BL
image, and some platforms have their own ones. They duplicate quite
similar code (and comments).

When we add some changes to linker scripts, we end up with touching
so many files. This is not nice in the maintainability perspective.

When you look at Linux kernel, the common code is macrofied in
include/asm-generic/vmlinux.lds.h, which is included from each arch
linker script, arch/*/kernel/vmlinux.lds.S

TF-A can follow this approach. Let's factor out the common code into
include/common/bl_common.ld.h

As a start point, this commit factors out the xlat_table section.

Change-Id: Ifa369e9b48e8e12702535d721cc2a16d12397895
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

show more ...

xlat_tables_v2: use ARRAY_SIZE in REGISTER_XLAT_CONTEXT_FULL_SPEC

With this, it is clearer that .base_table_entries and .tables_num
are the array size of .base_table and .tables, respectively.

Chan

xlat_tables_v2: use ARRAY_SIZE in REGISTER_XLAT_CONTEXT_FULL_SPEC

With this, it is clearer that .base_table_entries and .tables_num
are the array size of .base_table and .tables, respectively.

Change-Id: I634e65aba835ab9908cc3919355df6bc6e18d42a
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

show more ...

xlat_tables_v2: merge REGISTER_XLAT_CONTEXT_{FULL_SPEC,RO_BASE_TABLE}

xlat_tables_v2_helpers.h defines two quite similar macros,
REGISTER_XLAT_CONTEXT_FULL_SPEC and REGISTER_XLAT_CONTEXT_RO_BASE_TAB

xlat_tables_v2: merge REGISTER_XLAT_CONTEXT_{FULL_SPEC,RO_BASE_TABLE}

xlat_tables_v2_helpers.h defines two quite similar macros,
REGISTER_XLAT_CONTEXT_FULL_SPEC and REGISTER_XLAT_CONTEXT_RO_BASE_TABLE.

Only the difference is the section of _ctx_name##_base_xlat_table.

Parameterize it and unify these two macros.

The base xlat table goes into the .bss section by default.
If PLAT_RO_XLAT_TABLES is defined, it goes into the .rodata section.

Change-Id: I8b02f4da98f0c272e348a200cebd89f479099c55
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

show more ...

Merge changes from topic "sb/dualroot" into integration

* changes:
plat/arm: Pass cookie argument down to arm_get_rotpk_info()
plat/arm: Add support for dualroot CoT
plat/arm: Provide some PRO

Merge changes from topic "sb/dualroot" into integration

* changes:
plat/arm: Pass cookie argument down to arm_get_rotpk_info()
plat/arm: Add support for dualroot CoT
plat/arm: Provide some PROTK files for development

show more ...

Merge "Necessary fix in drivers to upgrade to mbedtls-2.18.0" into integration

Merge changes from topic "sb/dualroot" into integration

* changes:
Build system: Changes to drive cert_create for dualroot CoT
cert_create: Define the dualroot CoT
Introduce a new "dualroot" c

Merge changes from topic "sb/dualroot" into integration

* changes:
Build system: Changes to drive cert_create for dualroot CoT
cert_create: Define the dualroot CoT
Introduce a new "dualroot" chain of trust

show more ...

TF-A GICv3 driver: Separate GICD and GICR accessor functions

This patch provides separation of GICD, GICR accessor
functions and adds new macros for GICv3 registers access
as a preparation for GICv3

TF-A GICv3 driver: Separate GICD and GICR accessor functions

This patch provides separation of GICD, GICR accessor
functions and adds new macros for GICv3 registers access
as a preparation for GICv3.1 and GICv4 support.
NOTE: Platforms need to modify to include both
'gicdv3_helpers.c' and 'gicrv3_helpers.c' instead of the
single helper file previously.

Change-Id: I1641bd6d217d6eb7d1228be3c4177b2d556da60a
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

show more ...

Merge changes from topic "tegra-downstream-02182020" into integration

* changes:
Tegra186: store TZDRAM base/size to scratch registers
Tegra186: add SE support to generate SHA256 of TZRAM
Tegr

Merge changes from topic "tegra-downstream-02182020" into integration

* changes:
Tegra186: store TZDRAM base/size to scratch registers
Tegra186: add SE support to generate SHA256 of TZRAM
Tegra186: add support for bpmp_ipc driver
Tegra210: disable ERRATA_A57_829520
Tegra194: memctrl: add support for MIU4 and MIU5
Tegra194: memctrl: remove support to reconfigure MSS
Tegra: fiq_glue: remove bakery locks from interrupt handler
Tegra210: SE: add context save support
Tegra210: update the PMC blacklisted registers
Tegra: disable CPUACTLR access from lower exception levels
cpus: denver: fixup register used to store return address

show more ...

Tegra186: store TZDRAM base/size to scratch registers

This patch saves the TZDRAM base and size values to secure scratch
registers, for the WB0. The WB0 reads these values and uses them to
verify in

Tegra186: store TZDRAM base/size to scratch registers

This patch saves the TZDRAM base and size values to secure scratch
registers, for the WB0. The WB0 reads these values and uses them to
verify integrity of the TZDRAM aperture.

Change-Id: Ic70914cb958249f06cb58025a24d13734a85e16e
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra186: add SE support to generate SHA256 of TZRAM

The BL3-1 firmware code is stored in TZSRAM on Tegra186 platforms. This
memory loses power when we enter System Suspend and so its contents are
s

Tegra186: add SE support to generate SHA256 of TZRAM

The BL3-1 firmware code is stored in TZSRAM on Tegra186 platforms. This
memory loses power when we enter System Suspend and so its contents are
stored to TZDRAM, before entry. This opens up an attack vector where the
TZDRAM contents might be tampered with when we are in the System Suspend
mode. To mitigate this attack the SE engine calculates the hash of entire
TZSRAM and stores it in PMC scratch, before we copy data to TZDRAM. The
WB0 code will validate the TZDRAM and match the hash with the one in PMC
scratch.

This patch adds driver for the SE engine, with APIs to calculate the hash
and store SE SHA256 hash-result to PMC scratch registers.

Change-Id: Ib487d5629225d3d99bd35d44f0402d6d3cf27ddf
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>

show more ...

Tegra186: add support for bpmp_ipc driver

This patch enables the bpmp-ipc driver for Tegra186 platforms,
to ask BPMP firmware to toggle SE clock.

Change-Id: Ie63587346c4d9b7e54767dbee17d0139fa2818a

Tegra186: add support for bpmp_ipc driver

This patch enables the bpmp-ipc driver for Tegra186 platforms,
to ask BPMP firmware to toggle SE clock.

Change-Id: Ie63587346c4d9b7e54767dbee17d0139fa2818ae
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>

show more ...

Tegra210: disable ERRATA_A57_829520

ERRATA_A57_829520 disables "indirect branch prediction" for
EL1 on cpu reset, leading to 15% drop in CPU performance
with coremark benchmarks.

Tegra210 already h

Tegra210: disable ERRATA_A57_829520

ERRATA_A57_829520 disables "indirect branch prediction" for
EL1 on cpu reset, leading to 15% drop in CPU performance
with coremark benchmarks.

Tegra210 already has a hardware fix for ARM BUG#829520,so
this errata is not needed.

This patch disables the errata to get increased performance
numbers.

Change-Id: I0b42e8badd19a8101f6a55d80eb2d953597d3c20
Signed-off-by: Mithun Maragiri <mmaragiri@nvidia.com>

show more ...

Tegra194: memctrl: add support for MIU4 and MIU5

This patch adds support for memqual miu 4,5.

The MEMQUAL engine has miu0 to miu7 in which miu6 and
miu7 is hardwired to bypass SMMU. So only miu0 to

Tegra194: memctrl: add support for MIU4 and MIU5

This patch adds support for memqual miu 4,5.

The MEMQUAL engine has miu0 to miu7 in which miu6 and
miu7 is hardwired to bypass SMMU. So only miu0 to miu5
support is provided.

Change-Id: Ib350334eec521e65f395f1c3205e2cdaf464ebea
Signed-off-by: Pravin <pt@nvidia.com>

show more ...

Tegra194: memctrl: remove support to reconfigure MSS

As bpmp-fw is running at the same time as ATF, and
the mss client reconfiguration sequence involves performing
a hot flush resets on bpmp, there

Tegra194: memctrl: remove support to reconfigure MSS

As bpmp-fw is running at the same time as ATF, and
the mss client reconfiguration sequence involves performing
a hot flush resets on bpmp, there is a chance that bpmp-fw is
trying to perform accesses while the hot flush is active.

Therefore, the mss client reconfigure has been moved to
System Suspend resume fw and bootloader, and it can be
removed from here.

Change-Id: I34019ad12abea9681f5e180af6bc86f2c4c6fc74
Signed-off-by: Stefan Kristiansson <stefank@nvidia.com>

show more ...