plat/arm/board/arm_fpga: Enable basic BL31 port for an FPGA image

This adds the minimal functions and definitions to create a basic
BL31 port for an initial FPGA image, in order for the port to be
u

plat/arm/board/arm_fpga: Enable basic BL31 port for an FPGA image

This adds the minimal functions and definitions to create a basic
BL31 port for an initial FPGA image, in order for the port to be
uploaded to one the FPGA boards operated by an internal group within
Arm, such that BL31 runs as a payload for an image.

Future changes will enable the port for a wide range of system
configurations running on the FPGA boards to ensure compatibility with
multiple FPGA images.

It is expected that this will replace the FPGA fork of the Linux kernel
bootwrapper by performing similar secure-world initialization and setup
through the use of drivers and other well-established methods, before
passing control to the kernel, which will act as the BL33 payload and
run in EL2NS.

This change introduces a basic, loadable port with the console
initialized by setting the baud rate and base address of the UART as
configured by the Zeus image.

It is a BL31-only port, and RESET_TO_BL31 is enabled to reflect this.

Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: I1817ad81be00afddcdbbda1ab70eb697203178e2

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Merge "FVP: Add BL2 hash calculation in BL1" into integration

stm32mp1: use stm32mp_get_ddr_ns_size() function

Instead of using dt_get_ddr_size() and withdrawing the secure and shared
memory areas, use stm32mp_get_ddr_ns_size() function.

Change-Id: I5608fd787

stm32mp1: use stm32mp_get_ddr_ns_size() function

Instead of using dt_get_ddr_size() and withdrawing the secure and shared
memory areas, use stm32mp_get_ddr_ns_size() function.

Change-Id: I5608fd7873589ea0e1262ba7d2ee3e52b53d9a7d
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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stm32mp1: set XN attribute for some areas in BL2

DTB and BL32 area should not be set as executable in MMU during BL2
execution, hence set those areas as MT_RO_DATA.

Change-Id: I87c47a1e7fda761e541e

stm32mp1: set XN attribute for some areas in BL2

DTB and BL32 area should not be set as executable in MMU during BL2
execution, hence set those areas as MT_RO_DATA.

Change-Id: I87c47a1e7fda761e541ec98a5b294588384d31db
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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stm32mp1: dynamically map DDR later and non-cacheable during its test

A speculative accesses to DDR could be done whereas it was not reachable
and could lead to bus stall.
To correct this the dynami

stm32mp1: dynamically map DDR later and non-cacheable during its test

A speculative accesses to DDR could be done whereas it was not reachable
and could lead to bus stall.
To correct this the dynamic mapping in MMU is used.
A first mapping is done for DDR tests with MT_NON_CACHEABLE attribute,
once DDR access is setup. It is then unmapped and a new mapping DDR is done
with cacheable attribute (through MT_MEMORY) to speed-up BL33 (or OP-TEE)
load.

The disabling of cache during DDR tests is also removed, as now useless.
A call to new functions stm32mp_{,un}map_ddr_non_cacheable() is done
instead.

PLAT_XLAT_TABLES_DYNAMIC is activated globally as used in BL2 and BL32.

BL33 max size is also updated to take into account the secure and shared
memory areas. Those are used in OP-TEE case.

Change-Id: I22c48b4a48255ee264991c34ecbb15bfe87e67c3
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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stm32mp1: add a function to get non-secure DDR size

This function gets the DDR size from DT, and withdraws (if defined) the
sizes of secure DDR and shared memory areas.
This function also checks DT

stm32mp1: add a function to get non-secure DDR size

This function gets the DDR size from DT, and withdraws (if defined) the
sizes of secure DDR and shared memory areas.
This function also checks DT values fits the default DDR range.
This non-secure memory is available for BL33 and non-secure OS.

Change-Id: I162ae5e990a0f9b6b7d07e539de029f1d61a391b
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge "Fix warnings in porting-guide.rst" into integration

Merge "Tegra194: se: increase max. operation timeout to 1 second" into integration

Fix warnings in porting-guide.rst

Fix below warnings appeared in porting-guide.rst
WARNING: Title underline too short.

Change-Id: Ibc0eba0da72a53a5f9b61c49a8bf7a10b17bc3b8
Signed-off-by: Manish V B

Fix warnings in porting-guide.rst

Fix below warnings appeared in porting-guide.rst
WARNING: Title underline too short.

Change-Id: Ibc0eba0da72a53a5f9b61c49a8bf7a10b17bc3b8
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge changes I250c3aa1,Icf816053 into integration

* changes:
changelog: introduce SPMD, add secure partition loading and tooling
changelog: add debugfs functionality

changelog: introduce SPMD, add secure partition loading and tooling

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I250c3aa199d4e5efa68aa32bf5a1694835be56b7

changelog: add debugfs functionality

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Icf8160536c249c754b3dfac6f8f49ca7ad3bb0de

Tegra186: increase memory mapped regions

This patch increases MAX_MMAP_REGIONS to 30 to accommodate the
additional dynamic memory mapped region, during Trusty boot.

Signed-off-by: Varun Wadekar <vw

Tegra186: increase memory mapped regions

This patch increases MAX_MMAP_REGIONS to 30 to accommodate the
additional dynamic memory mapped region, during Trusty boot.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I461186a3aff5040f14715b87502fc5f1db3bea6e

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FVP: Add BL2 hash calculation in BL1

This patch provides support for measured boot by adding calculation
of BL2 image hash in BL1 and writing these data in TB_FW_CONFIG DTB.

Change-Id: Ic074a7ed19b

FVP: Add BL2 hash calculation in BL1

This patch provides support for measured boot by adding calculation
of BL2 image hash in BL1 and writing these data in TB_FW_CONFIG DTB.

Change-Id: Ic074a7ed19b14956719c271c805b35d147b7cec1
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

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Merge "Fix 'tautological-constant-compare' error" into integration

Fix 'tautological-constant-compare' error

Fixed below 'tautological-constant-compare' error when building the source
code with latest clang compiler <clang version 11.0.0>.

plat/common/plat_psci_co

Fix 'tautological-constant-compare' error

Fixed below 'tautological-constant-compare' error when building the source
code with latest clang compiler <clang version 11.0.0>.

plat/common/plat_psci_common.c:36:2:
error: converting the result of '<<' to a boolean always evaluates
to true [-Werror,-Wtautological-constant-compare]
PMF_STORE_ENABLE)
^
include/lib/pmf/pmf.h:28:29: note: expanded from macro 'PMF_STORE_ENABLE'
PMF_STORE_ENABLE (1 << 0)

This error is observed beacuse of CASSERT placed in
"PMF_DEFINE_CAPTURE_TIMESTAMP" which do below stuff:
CASSERT(_flags, select_proper_config);
where _flags = PMF_STORE_ENABLE (1 << 0) which always results true.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ifa82ea202496a23fdf1d27ea1798d1f1b583a021

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Merge "spm: Add spci manifest binding document" into integration

Merge "fconf: Clean Arm IO" into integration

Merge "plat/sgi: Bump bl1 RW limit" into integration

Merge "corstone700: updating the kernel arguments to support initramfs" into integration

Merge "context: TPIDR_EL2 register not saved/restored" into integration

corstone700: updating the kernel arguments to support initramfs

In the context of enabling initramfs this change makes
the kernel arguments compatible with the initramfs requirements

Change-Id: Ifa

corstone700: updating the kernel arguments to support initramfs

In the context of enabling initramfs this change makes
the kernel arguments compatible with the initramfs requirements

Change-Id: Ifa955a5790ae1398fd8ad9ca1c8272f019c121a6
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>

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Merge "spmd: skip loading of secure partitions on pre-v8.4 platforms" into integration

Tegra194: se: increase max. operation timeout to 1 second

This patch increases the maximum timeout value for SE operation
completion to 1 second. This takes care of some corner cases where
an operat

Tegra194: se: increase max. operation timeout to 1 second

This patch increases the maximum timeout value for SE operation
completion to 1 second. This takes care of some corner cases where
an operation might take more time than the previous timeout value
of 100ms.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I0012448ba372a8bb0e156df7dfe49d7de6d21a68

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spmd: skip loading of secure partitions on pre-v8.4 platforms

When SPD=spmd and SPMD_SPM_AT_SEL2=0, that is SPMC sits at S-EL1
then there is no need for TF-A to load secure partitions individually.

spmd: skip loading of secure partitions on pre-v8.4 platforms

When SPD=spmd and SPMD_SPM_AT_SEL2=0, that is SPMC sits at S-EL1
then there is no need for TF-A to load secure partitions individually.
In this configuration, SPMC handles secure partition loading at
S-EL1/EL0 levels.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I06a0d88a4811274a8c347ce57b56bb5f64e345df

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