Merge changes I1e816dc9,I6550f2b9 into integration

* changes:
feat(mt8189): add UFS driver support
fix(mediatek): fix mtcmos build failure

fix(versal2): move plat_core_pos_by_mpidr to asm

In the current implementation, plat_core_pos_by_mpidr() is defined in
C.When BL31 is compiled with Armclang, a call to plat_core_pos_by_mpidr()
from

fix(versal2): move plat_core_pos_by_mpidr to asm

In the current implementation, plat_core_pos_by_mpidr() is defined in
C.When BL31 is compiled with Armclang, a call to plat_core_pos_by_mpidr()
from plat_my_core_pos() results in the return address stored in register
x30 becoming invalid and register x9 (used later) ends up with the value
0x0. Consequently, the CPU branches to address 0x0, triggering a
synchronous exception. TF-A then invokes the BHB flush code before
resuming execution. However, since the stack is not properly initialized
at this stage, the system eventually enters plat_panic_handler().
In the updated implementation, the platform_get_core_pos() function
is redefined in assembly to provide tighter control during early boot
stages. The MPIDR_EL1 register contains three affinity levels: Aff0
(bits [0:7]), Aff1 (bits [8:15]), and Aff2 (bits [16:23]). In this
assembly function, the core ID is extracted from Aff1
(MPIDR_AFF1_SHIFT), and the cluster ID from Aff2 (MPIDR_AFF2_SHIFT).
cluster/core ID calculation. The macro PLATFORM_MPIDR_AFFINITY_MASK
introduced to mask MPIDR_EL1 register.

Change-Id: Id532bbcd68f18e87ceba01c8f961d8c15962a1a3
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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fix(versal-net): move plat_core_pos_by_mpidr to asm

In the current implementation, plat_core_pos_by_mpidr() is defined
in C. When BL31 is compiled with Armclang, a call to
plat_core_pos_by_mpidr() f

fix(versal-net): move plat_core_pos_by_mpidr to asm

In the current implementation, plat_core_pos_by_mpidr() is defined
in C. When BL31 is compiled with Armclang, a call to
plat_core_pos_by_mpidr() from plat_my_core_pos() results in the
return address stored in register x30 becoming invalid and register
x9 (used later) ends up with the value 0x0. Consequently, the CPU
branches to address 0x0, triggering a synchronous exception. TF-A
then invokes the BHB flush code before resuming execution. However,
since the stack is not properly initialized at this stage, the system
eventually enters plat_panic_handler(). In the updated implementation,
the platform_get_core_pos() function is redefined in assembly to
provide tighter control during early boot stages. The MPIDR_EL1
register contains three affinity levels: Aff0 (bits [0:7]), Aff1
(bits [8:15]), and Aff2 (bits [16:23]). In this assembly function,
the core ID is extracted from Aff1 (MPIDR_AFF1_SHIFT), and the cluster
ID from Aff2 (MPIDR_AFF2_SHIFT). The macro PLATFORM_MPIDR_AFFINITY_MASK
introduced to mask MPIDR_EL1 register.

Change-Id: I090ea107c27dfa643431a97d15556c98f721b2e4
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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feat(mt8189): add SPM low power mode

1. Add enable PERI AO.
2. Add infra bus parity re-init.
3. SPM enter 26M.

Signed-off-by: Kun Lu <kun.lu@mediatek.com>
Change-Id: Ifbc2d87be47f106857db17c23fb968

feat(mt8189): add SPM low power mode

1. Add enable PERI AO.
2. Add infra bus parity re-init.
3. SPM enter 26M.

Signed-off-by: Kun Lu <kun.lu@mediatek.com>
Change-Id: Ifbc2d87be47f106857db17c23fb968aafec150d2

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Merge "fix(versal): update integer const with suffix U" into integration

feat(mt8189): add UFS driver support

Add UFS driver support in platform.mk.

Signed-off-by: Cloud Zhang <cloud.zhang@mediatek.corp-partner.google.com>
Change-Id: I1e816dc9c21e856ae50d4409f13b1a8598b

feat(mt8189): add UFS driver support

Add UFS driver support in platform.mk.

Signed-off-by: Cloud Zhang <cloud.zhang@mediatek.corp-partner.google.com>
Change-Id: I1e816dc9c21e856ae50d4409f13b1a8598b6fb3f

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fix(mediatek): fix mtcmos build failure

Fix mtcmos build failure due to lack of definition:
plat/mediatek/drivers/mtcmos/mtcmos_common.h:16:9:
error: unknown type name 'uint32_t'
plat/mediatek/drive

fix(mediatek): fix mtcmos build failure

Fix mtcmos build failure due to lack of definition:
plat/mediatek/drivers/mtcmos/mtcmos_common.h:16:9:
error: unknown type name 'uint32_t'
plat/mediatek/drivers/mtcmos/mt8189/mtcmos.h:31:41:
error: implicit declaration of function 'BIT'

Signed-off-by: irving-ch-lin <irving-ch.lin@mediatek.com>
Change-Id: I6550f2b99d43c72471d481eff081affe098144dd

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fix(smccc): resolve caller world confusion

TF-A checks the SMC caller world using is_caller_secure,
is_caller_non_secure and is_caller_realm macros. Until
realm world was introduced it was fine to u

fix(smccc): resolve caller world confusion

TF-A checks the SMC caller world using is_caller_secure,
is_caller_non_secure and is_caller_realm macros. Until
realm world was introduced it was fine to use a pattern like

if (is_caller_non_secure(flags))
return DENY;

// Handle secure call
secure_operation();

is_caller_non_secure would be false for a realm caller, so this pattern
treats this like a secure world caller. This patch fixes
improper use of is_caller_non_secure and is_caller_secure
to handle realm world caller properly.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I60b125853183ac2ac15277f06d2efb7f3a9d3977

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Merge changes from topic "Add-i.MX94/95-suport" into integration

* changes:
docs(maintainers): add i.MX9 to maintained paths
feat(imx94): add initial support for imx94
feat(imx95): add optee s

Merge changes from topic "Add-i.MX94/95-suport" into integration

* changes:
docs(maintainers): add i.MX9 to maintained paths
feat(imx94): add initial support for imx94
feat(imx95): add optee support
feat(imx95): support trusty os
feat(imx95): implement a semaphore for GIC quiescing
feat(imx95): add initial support for i.MX95
feat(imx9): add necessary ele api call support
feat(imx9): add imx9 common code base
refactor(imx): drop the __dead2 attribute
fix(imx): add static attribute for platform specific gic struct
feat(gic): change gic_cpuif_enable/disable to weak
feat(scmi): add i.MX9 SCMI vendor CPU protocol
feat(scmi): add base protocol agent API
feat(scmi): update version to 3.0
build(changelog): update for imx94/95 support

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fix(versal): update integer const with suffix U

Versal: standardize unsigned integer constants to use suffix.
Updated all unsigned integer constants in the Versal platform
to use the unsigned suffix

fix(versal): update integer const with suffix U

Versal: standardize unsigned integer constants to use suffix.
Updated all unsigned integer constants in the Versal platform
to use the unsigned suffix (e.g., `10U`)
instead of the prefix style (e.g., `U(10)`) for consistency.

Change-Id: Ie4d20c18cccede20062d6189c1024acfb3a3dce0
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(psci): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.
Enclosed statement body w

fix(psci): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.
Enclosed statement body within the curly braces.

Change-Id: Ida2460b7fe6f27b23382a1259a5ac93fe36bd48d
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>
Signed-off-by: Suraj Kakade <suraj.hanumantkakade@amd.com>

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fix(cm): use safe casting in memcpy

This corrects the MISRA violation C2012-21.15:
Both gp_regs and ep->args were cast to the correct pointer types to
avoid incompatible argument types in memcpy().

fix(cm): use safe casting in memcpy

This corrects the MISRA violation C2012-21.15:
Both gp_regs and ep->args were cast to the correct pointer types to
avoid incompatible argument types in memcpy(). This fix ensures type
compatibility and adheres to MISRA 21.15, which disallows implicit
casting between unrelated types

Change-Id: Iad1d78574e423b46934a5978bdcbe2d5fb78e910
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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Merge "fix(dcc): typecast operands to match data type" into integration

Merge changes from topic "xlnx_runtime_console" into integration

* changes:
fix(versal2): runtime console in debug mode
fix(versal-net): runtime console in debug mode
fix(versal): runtime cons

Merge changes from topic "xlnx_runtime_console" into integration

* changes:
fix(versal2): runtime console in debug mode
fix(versal-net): runtime console in debug mode
fix(versal): runtime console in debug mode
fix(zynqmp): runtime console in debug mode

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Merge "fix(versal-net): add fallback on handoff failure" into integration

fix(gicv3): typecast operands to match data type

This corrects the MISRA violation C2012-10.1:
Operands shall not be of an inappropriate essential type.
The condition is explicitly checked against 0

fix(gicv3): typecast operands to match data type

This corrects the MISRA violation C2012-10.1:
Operands shall not be of an inappropriate essential type.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: Icd480587b74c0e0a818498b680666ed43e94fef8
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(gicv3): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.Enclosed statement body w

fix(gicv3): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.Enclosed statement body within the curly
braces.

Change-Id: I657780b0e322a0aff990390a8dfc1af56dfd5c1d
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(gicv3): fix misra violation 12.1

This corrects the MISRA violation C2012-12.1:
When an expression contains multiple operators, use compound
assignment operator or curley braces to avoid unexpect

fix(gicv3): fix misra violation 12.1

This corrects the MISRA violation C2012-12.1:
When an expression contains multiple operators, use compound
assignment operator or curley braces to avoid unexpected behavior
due to operator precedence and which improves the readibility and
maintainability.

Change-Id: I8d09f136faae2869fc1ef2d6eb46de035b7e6a1e
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(gicv3): match function definition and declaration

This corrects the MISRA violation C2012-8.3:
change the type/qualifer of function parameter as per the functional
decleration. unction declerati

fix(gicv3): match function definition and declaration

This corrects the MISRA violation C2012-8.3:
change the type/qualifer of function parameter as per the functional
decleration. unction decleration and definition should be match to
avoid conflicts.

Change-Id: Ic6cff6719a38dffe78e4756d3bb7cf32512c5344
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(gicv3): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a di

fix(gicv3): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: Id802961c24a57eea7dd928e2278d015a8747a4c5
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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feat(fwu): create flag for BL2 separation

Adding a flag for BL2 separation in common
Makefile, for the usage of non FVP platform

Change-Id: I45ecb6833cdbc4873ffe460fd448814d81d6fa4d
Signed-off-by:

feat(fwu): create flag for BL2 separation

Adding a flag for BL2 separation in common
Makefile, for the usage of non FVP platform

Change-Id: I45ecb6833cdbc4873ffe460fd448814d81d6fa4d
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge "fix(intel): add missing cache flush operation for hmac" into integration

fix(neoverse-rd): add console initialisation to BL31

Neoverse-RD currently neglects to initialise the console in BL31. This
change adds the missing initialisation routine.

Change-Id: I946485f4dd857

fix(neoverse-rd): add console initialisation to BL31

Neoverse-RD currently neglects to initialise the console in BL31. This
change adds the missing initialisation routine.

Change-Id: I946485f4dd857240208653e237a83e71073c33ff
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(arm): re-enable console by default in BL31

In c997a8d, the common `arm_bl31_early_platform_setup` function
underwent a consolidation of two large preprocessor branches that were
conditional on w

fix(arm): re-enable console by default in BL31

In c997a8d, the common `arm_bl31_early_platform_setup` function
underwent a consolidation of two large preprocessor branches that were
conditional on whether or not Transfer List support is enabled.

This function would initialise the console via `arm_console_boot_init`
*only* if Transfer List support was disabled. During the consolidation,
this call was removed, such that the behaviour was the same for both
branches.

However, the common `bl31_early_platform_setup2` implementation was not
updated to reflect this change, and so platforms that a) relied on this
common implementation and b) did not enable Transfer List support no
longer initialise the console in BL31.

This change ensures that the common implementation correctly initialises
the console during early BL31 boot.

Change-Id: I332af3932ac70382fbf7a5434c0008807f38f86c
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge "fix(intel): iossm v2 enhancement refactor" into integration