Merge "feat(gic): make IRQ groups optional" into integration

Merge changes from topic "hm/handoff-cot" into integration

* changes:
docs(fconf): streamline TB_FW_CONFIG bindings
refactor(fconf): use macro to set image info

fix(intel): remove wfi polling when performing cpu on

Polling the WFI status produces vague result as
the secondary CPU will keep changing it's states.

Removing the polling WFI code as this will ca

fix(intel): remove wfi polling when performing cpu on

Polling the WFI status produces vague result as
the secondary CPU will keep changing it's states.

Removing the polling WFI code as this will cause
polling timeout since the CPU state is uncertain.

The CPU ON function will still work by removing this
check.

Change-Id: I1bb556a83ca16e122dfa35343de3e7cc39c5b678
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): fix socfpga_psci for cpu on off function

Fix for CPU ON / OFF Function calling from Linux Kernel.

Change-Id: Ie450acf7e537ed60ef4b2e8d785e62d94e52482f
Signed-off-by: Boon Khai Ng <boon.

fix(intel): fix socfpga_psci for cpu on off function

Fix for CPU ON / OFF Function calling from Linux Kernel.

Change-Id: Ie450acf7e537ed60ef4b2e8d785e62d94e52482f
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge changes from topic "ar/soc_name" into integration

* changes:
feat(fvp): add SoC name support to FVP
feat(smccc): add SoC name support to SMCCC_ARCH_SOC_ID

Merge "feat(juno): support StandaloneMm" into integration

feat(fvp): add SoC name support to FVP

This patch adds support in the FVP platform for the SoC name
field in SMCCC_ARCH_SOC_ID. The returned string is formatted as:

"Arm Platform Revision <SoC Re

feat(fvp): add SoC name support to FVP

This patch adds support in the FVP platform for the SoC name
field in SMCCC_ARCH_SOC_ID. The returned string is formatted as:

"Arm Platform Revision <SoC Revision>"

This adheres to the guideline that the SoC name must not expose
information beyond what is already captured in <SoC Version, SoC
Revision>.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I83da745a754c6fc8f9fa27ee8d8024d6692d3409

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feat(smccc): add SoC name support to SMCCC_ARCH_SOC_ID

This patch adds support for getting the SoC name string
using the SMCCC_ARCH_SOC_ID interface. The SoC name query
was introduced in SMCCC versi

feat(smccc): add SoC name support to SMCCC_ARCH_SOC_ID

This patch adds support for getting the SoC name string
using the SMCCC_ARCH_SOC_ID interface. The SoC name query
was introduced in SMCCC version 1.6. It is available only
through SMC64 calls.

A new function ID, SMCCC_GET_SOC_NAME, is added. It returns
the SoC name as a null-terminated ASCII string, spread across
registers X1 to X17 in little endian order.
The total length is 136 bytes, including the null byte.
Any space after the null terminator is filled
with zeros.

A platform hook plat_get_soc_name() is added to return the
SoC name. A weak default version is also provided that returns
SMC_ARCH_CALL_NOT_SUPPORTED for platforms that do not support
this feature.

The name should follow the SMCCC rule that it must not expose
any information that is not already reported
by the SoC version and revision calls.

Reference: https://developer.arm.com/documentation/den0028/latest/

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Idc69997c509bcbfb1cecb38ed1003b29627ade4b

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Merge "feat(mt8189): add support display driver" into integration

Merge changes I3e086865,I47f05a9f,Iee495571 into integration

* changes:
fix(cpufeat): update FEAT_PAUTH's feat detect line to tri-state
fix(cpufeat): do feature detection before feature enableme

Merge changes I3e086865,I47f05a9f,Iee495571 into integration

* changes:
fix(cpufeat): update FEAT_PAUTH's feat detect line to tri-state
fix(cpufeat): do feature detection before feature enablement
feat(cpufeat): do feature detection on secondary cores too

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fix(intel): configure usb3 system manager reg in TFA

Reset pulse override bit needs to be set for successful
reset staggering pulse generation.

The bit one of power over-current field actually refl

fix(intel): configure usb3 system manager reg in TFA

Reset pulse override bit needs to be set for successful
reset staggering pulse generation.

The bit one of power over-current field actually reflects
PIPE power present signal. This bit needs to be set to
avoid providing false information about VBus to the
HPS controller.

Change-Id: I123e2ec7c8ceaa15f47f90460fae5a325741dd10
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): update TFA to patch for Linux 6.12 rebase warning message

On MMU-500 r2p0+ (used in newer SoCFPGA platforms),
we need to clear the SMMU_sACR.CACHE_LOCK bit
so the normal world can write

fix(intel): update TFA to patch for Linux 6.12 rebase warning message

On MMU-500 r2p0+ (used in newer SoCFPGA platforms),
we need to clear the SMMU_sACR.CACHE_LOCK bit
so the normal world can write to SMMU_CBn_ACTLR.

Change-Id: I0d0d227950508a2969fe0fe2eddbe6894efe54bc
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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feat(juno): support StandaloneMm

Support StandaloneMm in Juno platform.
When Juno using StandaloneMm, last 2MB area of norflash0 is used by
StandaloneMm only and that area shouldn't be accessed by n

feat(juno): support StandaloneMm

Support StandaloneMm in Juno platform.
When Juno using StandaloneMm, last 2MB area of norflash0 is used by
StandaloneMm only and that area shouldn't be accessed by normal world.
For this, add last 2MB area of norflash0 in TZC setting.

Change-Id: Ice63f13c34f452f2b8cb93ee88dc666632b84248
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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fix(cpufeat): update FEAT_PAUTH's feat detect line to tri-state

Since patch 8d9f5f258, FEAT_PAUTH has supported the tri-state framework.
This part was missed, update it.

Change-Id: I3e086865df4d852

fix(cpufeat): update FEAT_PAUTH's feat detect line to tri-state

Since patch 8d9f5f258, FEAT_PAUTH has supported the tri-state framework.
This part was missed, update it.

Change-Id: I3e086865df4d852e9d31a04cd8150d9d8a4dd2b8
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(cpufeat): do feature detection before feature enablement

Situations where feature configuration does not reflect hardware's
features can cause unhandled exceptions at EL3. Feature detection is
m

fix(cpufeat): do feature detection before feature enablement

Situations where feature configuration does not reflect hardware's
features can cause unhandled exceptions at EL3. Feature detection is
meant to guard against these errors by checking hardware against the
configuration. For this to happen though, feature detection has to
happen before these unhandled exceptions have had a chance to happen.

Change-Id: I47f05a9f01321e011623083afb638552311ed013
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): do feature detection on secondary cores too

Feature detection currently only happens on the boot core, however, it
is possible to have asymmetry between cores. TF-A supports limited s

feat(cpufeat): do feature detection on secondary cores too

Feature detection currently only happens on the boot core, however, it
is possible to have asymmetry between cores. TF-A supports limited such
configurations so it should check secondary cores too.

Change-Id: Iee4955714685be9ae6a017af4a6c284e835ff299
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(imx8m): don't reconfigure default region0

The current code and comments can be read as: "The TZC-380 region 0 can
be configured in size and attributes". This is not true, only the
attributes can

fix(imx8m): don't reconfigure default region0

The current code and comments can be read as: "The TZC-380 region 0 can
be configured in size and attributes". This is not true, only the
attributes can be set.

The TZC-380 region 0 is the TZC default (fallback) region. This region
is used if access to a certain DRAM address was done which isn't covered
by any other region (see [1] for more information). Region 0 covers the
complete AXI space from 0x0 to AXI-bus width. The access is secure-only
after reset.

The TZC-380 is not memory alias aware (see [1] for more information) and
due to the DDR controller, the i.MX8M allows memory alias access.

Configuring region 0 as secure + non-secure RW access opens the
potential security risk of allowing access to secure only memory e.g.
TEE memory area if the TEE didn't configure all memory aliases for its
memory. In such case region 0 is used as fallback if an attackers access
the TEE memory via memory aliases.

To fix this don't touch the TZC-380 at all. The TZC-380 is bypassed
by default if a platform doesn't require a TEE. If the platform requires
a TEE, the TEE is the one which knows the secure areas so let the TEE
configure the TZC-380 accordingly.

Furthmore, since commits:
- 0324081af010 ("feat(imx8mp): restrict peripheral access to secure
world")
- 1156c76361c1 ("feat(imx8mm): restrict peripheral access to secure
world")
the access is limited to the TEE too.

[1] https://developer.arm.com/documentation/ddi0431/c

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I0a0f9b5ad0017f38d767f583d7765a2f79861589

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Merge changes from topic "bk/pabandon_cleanup" into integration

* changes:
feat(cpus): add pabandon support to the Alto cpu
feat(psci): optimise clock init on a pabandon
feat(psci): check that

Merge changes from topic "bk/pabandon_cleanup" into integration

* changes:
feat(cpus): add pabandon support to the Alto cpu
feat(psci): optimise clock init on a pabandon
feat(psci): check that CPUs handled a pabandon
feat(psci): make pabandon support generic
refactor(psci): unify coherency exit between AArch64 and AArch32
refactor(psci): absorb psci_power_down_wfi() into common code
refactor(platforms): remove usage of psci_power_down_wfi
fix(cm): disable SPE/TRBE correctly

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fix(arm-drivers): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.Enclosed statement

fix(arm-drivers): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.Enclosed statement body within the curly
braces.

Change-Id: I0e2ef3c2210816d1da09671157f23d42e493e356
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(arm): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a diff

fix(arm): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: I04089721d124a2701e10d3f6e0ed8f82e3f6e0b3
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(arm-drivers): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Chan

fix(arm-drivers): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change-Id: I10c42f7b1ec5264a19feb7d666c2661bfdb45975
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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Merge "fix(fdts): remove extra members in PCI interrupt-map" into integration

fix(fdts): remove extra members in PCI interrupt-map

The FVP PCI interrupt-map DT entries are wrong and has extra members.
This patch removes the same.

Change-Id: I892cb2e2b8c6a57aec3007518d4f65014

fix(fdts): remove extra members in PCI interrupt-map

The FVP PCI interrupt-map DT entries are wrong and has extra members.
This patch removes the same.

Change-Id: I892cb2e2b8c6a57aec3007518d4f650146934283
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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Merge changes from topic "ffa_mem_perm_get_update" into integration

* changes:
feat(spm): update MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64 interface
feat(el3-spmc): update FFA_MEM_PERM_GET interface

feat(cpus): add pabandon support to the Alto cpu

Alto supports powerdown abandon. That support has flown under the radar
so add it in the same way as other pabandon CPUs.

Change-Id: I15f9e8cd77bf5a

feat(cpus): add pabandon support to the Alto cpu

Alto supports powerdown abandon. That support has flown under the radar
so add it in the same way as other pabandon CPUs.

Change-Id: I15f9e8cd77bf5aa23df8e548eb3d35d5c1f4eb2d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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