1 /*
2 * Copyright (c) 2025, Mediatek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <common/debug.h>
8 #include <lib/mmio.h>
9
10 #include <mt_spm_hwreq.h>
11 #include <mt_spm_reg.h>
12 #include <platform_def.h>
13
spm_hwcg_index2res(uint32_t idx)14 static uint32_t spm_hwcg_index2res(uint32_t idx)
15 {
16 uint32_t res;
17
18 if (idx >= HWCG_MAX)
19 return 0;
20
21 switch (idx) {
22 case HWCG_DDREN:
23 res = (MT_SPM_DRAM_S0 | MT_SPM_DRAM_S1 | MT_SPM_EMI);
24 break;
25 case HWCG_VRF18:
26 res = MT_SPM_SYSPLL;
27 break;
28 case HWCG_INFRA:
29 res = MT_SPM_INFRA;
30 break;
31 case HWCG_PMIC:
32 res = MT_SPM_PMIC;
33 break;
34 case HWCG_F26M:
35 res = MT_SPM_26M;
36 break;
37 case HWCG_VCORE:
38 res = MT_SPM_VCORE;
39 break;
40 default:
41 res = 0;
42 }
43 return res;
44 }
45
spm_hwcg_ctrl_get(struct spm_hwcg_info * info,enum spm_hwcg_setting type)46 static uint32_t spm_hwcg_ctrl_get(struct spm_hwcg_info *info,
47 enum spm_hwcg_setting type)
48 {
49 uint32_t reg = 0;
50
51 if (!info)
52 return 0;
53
54 switch (type) {
55 case HWCG_PWR:
56 reg = info->pwr;
57 break;
58 case HWCG_PWR_MSB:
59 reg = info->pwr_msb;
60 break;
61 default:
62 reg = info->module_busy;
63 break;
64 }
65 return reg;
66 }
67
__spm_hwcg_ctrl(struct spm_hwcg_info * info,enum spm_hwcg_setting type,uint32_t is_set,uint32_t val)68 static void __spm_hwcg_ctrl(struct spm_hwcg_info *info,
69 enum spm_hwcg_setting type, uint32_t is_set,
70 uint32_t val)
71 {
72 uint32_t reg;
73
74 reg = spm_hwcg_ctrl_get(info, type);
75
76 if (!reg)
77 return;
78
79 if (is_set)
80 mmio_setbits_32(reg, val);
81 else
82 mmio_clrbits_32(reg, val);
83 }
84
spm_hwcg_ctrl(uint32_t res,enum spm_hwcg_setting type,uint32_t is_set,uint32_t val)85 void spm_hwcg_ctrl(uint32_t res, enum spm_hwcg_setting type, uint32_t is_set,
86 uint32_t val)
87 {
88 struct spm_hwcg_info info;
89
90 if (res & (MT_SPM_DRAM_S0 | MT_SPM_DRAM_S1 | MT_SPM_EMI))
91 DECLARE_HWCG_REG(DDREN, info);
92 else if (res & MT_SPM_SYSPLL)
93 DECLARE_HWCG_REG(VRF18, info);
94 else if (res & MT_SPM_INFRA)
95 DECLARE_HWCG_REG(INFRA, info);
96 else if (res & MT_SPM_PMIC)
97 DECLARE_HWCG_REG(PMIC, info);
98 else if (res & MT_SPM_26M)
99 DECLARE_HWCG_REG(F26M, info);
100 else if (res & MT_SPM_VCORE)
101 DECLARE_HWCG_REG(VCORE, info);
102 else
103 HWCG_INFO_INIT(info);
104
105 if (info.pwr)
106 __spm_hwcg_ctrl(&info, type, is_set, val);
107 }
108
spm_hwcg_ctrl_by_index(uint32_t idx,enum spm_hwcg_setting type,uint32_t is_set,uint32_t val)109 void spm_hwcg_ctrl_by_index(uint32_t idx, enum spm_hwcg_setting type,
110 uint32_t is_set, uint32_t val)
111 {
112 uint32_t res = spm_hwcg_index2res(idx);
113
114 if (res)
115 spm_hwcg_ctrl(res, type, is_set, val);
116 }
117
spm_hwcg_mask_get(uint32_t res,enum spm_hwcg_setting type)118 static uint32_t spm_hwcg_mask_get(uint32_t res, enum spm_hwcg_setting type)
119 {
120 struct spm_hwcg_info info;
121 uint32_t raw_val = 0, reg = 0;
122
123 if (res & (MT_SPM_DRAM_S0 | MT_SPM_DRAM_S1 | MT_SPM_EMI))
124 DECLARE_HWCG_REG(DDREN, info);
125 else if (res & MT_SPM_SYSPLL)
126 DECLARE_HWCG_REG(VRF18, info);
127 else if (res & MT_SPM_INFRA)
128 DECLARE_HWCG_REG(INFRA, info);
129 else if (res & MT_SPM_PMIC)
130 DECLARE_HWCG_REG(PMIC, info);
131 else if (res & MT_SPM_26M)
132 DECLARE_HWCG_REG(F26M, info);
133 else if (res & MT_SPM_VCORE)
134 DECLARE_HWCG_REG(VCORE, info);
135 else
136 HWCG_INFO_INIT(info);
137
138 if (!info.pwr)
139 return 0;
140
141 reg = spm_hwcg_ctrl_get(&info, type);
142
143 if (!reg)
144 return 0;
145
146 raw_val = ~mmio_read_32(reg);
147
148 return raw_val;
149 }
150
spm_hwcg_get_default(uint32_t res,enum spm_hwcg_setting type)151 static uint32_t spm_hwcg_get_default(uint32_t res, enum spm_hwcg_setting type)
152 {
153 struct spm_hwcg_info info;
154
155 if (res & (MT_SPM_DRAM_S0 | MT_SPM_DRAM_S1 | MT_SPM_EMI))
156 DECLARE_HWCG_DEFAULT(DDREN, info);
157 else if (res & MT_SPM_SYSPLL)
158 DECLARE_HWCG_DEFAULT(VRF18, info);
159 else if (res & MT_SPM_INFRA)
160 DECLARE_HWCG_DEFAULT(INFRA, info);
161 else if (res & MT_SPM_PMIC)
162 DECLARE_HWCG_DEFAULT(PMIC, info);
163 else if (res & MT_SPM_26M)
164 DECLARE_HWCG_DEFAULT(F26M, info);
165 else if (res & MT_SPM_VCORE)
166 DECLARE_HWCG_DEFAULT(VCORE, info);
167 else
168 HWCG_INFO_INIT(info);
169
170 if (!info.pwr)
171 return 0;
172
173 return spm_hwcg_ctrl_get(&info, type);
174 }
175
176 #define _APMIXEDSYS(ofs) (APMIXEDSYS + ofs)
177 #define PLL_UNIV _APMIXEDSYS(0x314)
178 #define PLL_MM _APMIXEDSYS(0x324)
179 #define PLL_MSDC _APMIXEDSYS(0x35C)
180 #define PLL_UFS _APMIXEDSYS(0x36C)
181 #define PLLEN_ALL _APMIXEDSYS(0x070)
182 #define PLL_UNIV_MERG BIT(5)
183 #define PLL_MM_MERG BIT(3)
184 #define PLL_MSDC_MERG BIT(4)
185 #define PLL_UFS_MERG BIT(2)
186
spm_hwcg_get_status(uint32_t idx,enum spm_hwcg_setting type)187 uint32_t spm_hwcg_get_status(uint32_t idx, enum spm_hwcg_setting type)
188 {
189 uint32_t val = 0;
190 uint32_t pllen_all = 0;
191
192 switch (type) {
193 case HWCG_PWR:
194 val = mmio_read_32(PWR_STATUS);
195 break;
196 case HWCG_PWR_MSB:
197 val = mmio_read_32(PWR_STATUS_MSB);
198 break;
199 default:
200 pllen_all = mmio_read_32(PLLEN_ALL);
201
202 if ((mmio_read_32(PLL_UNIV) & 0x1) ||
203 (pllen_all & PLL_UNIV_MERG))
204 val |= BIT(HWCG_MODULE_UNIVPLL);
205 if ((mmio_read_32(PLL_MSDC) & 0x1) ||
206 (pllen_all & PLL_MSDC_MERG))
207 val |= BIT(HWCG_MODULE_MSDCPLL);
208 if ((mmio_read_32(PLL_UFS) & 0x1) || (pllen_all & PLL_UFS_MERG))
209 val |= BIT(HWCG_MODULE_UFSPLL);
210 if ((mmio_read_32(PLL_MM) & 0x1) || (pllen_all & PLL_MM_MERG))
211 val |= BIT(HWCG_MODULE_MMPLL);
212 break;
213 }
214 return val;
215 }
216
spm_hwcg_get_setting(uint32_t res,enum spm_hwcg_sta_type sta_type,enum spm_hwcg_setting type,struct spm_hwcg_sta * sta)217 int spm_hwcg_get_setting(uint32_t res, enum spm_hwcg_sta_type sta_type,
218 enum spm_hwcg_setting type, struct spm_hwcg_sta *sta)
219 {
220 int ret = 0;
221
222 if (!sta)
223 return -1;
224
225 switch (sta_type) {
226 case HWCG_STA_DEFAULT_MASK:
227 sta->sta = spm_hwcg_get_default(res, type);
228 break;
229 case HWCG_STA_MASK:
230 sta->sta = spm_hwcg_mask_get(res, type);
231 break;
232 default:
233 ret = -1;
234 MT_SPM_HW_CG_STA_INIT(sta);
235 break;
236 }
237 return ret;
238 }
239
spm_hwcg_get_setting_by_index(uint32_t idx,enum spm_hwcg_sta_type sta_type,enum spm_hwcg_setting type,struct spm_hwcg_sta * sta)240 int spm_hwcg_get_setting_by_index(uint32_t idx, enum spm_hwcg_sta_type sta_type,
241 enum spm_hwcg_setting type,
242 struct spm_hwcg_sta *sta)
243 {
244 uint32_t res = spm_hwcg_index2res(idx);
245
246 return spm_hwcg_get_setting(res, sta_type, type, sta);
247 }
248
spm_infra_swcg_init(void)249 static void spm_infra_swcg_init(void)
250 {
251 mmio_write_32(INFRA_SW_CG_0_MASK, ~INFRA_SW_CG_MB);
252 mmio_write_32(INFRA_SW_CG_1_MASK, ~INFRA_SW_CG_MB);
253 mmio_write_32(INFRA_SW_CG_2_MASK, ~INFRA_SW_CG_MB);
254 mmio_write_32(INFRA_SW_CG_3_MASK, ~INFRA_SW_CG_MB);
255 mmio_write_32(INFRA_SW_CG_4_MASK, ~INFRA_SW_CG_MB);
256 }
257
spm_hwcg_init(void)258 static void spm_hwcg_init(void)
259 {
260 /* HW CG for ddren, apsrc, emi resource req */
261 mmio_write_32(REG_PWR_STATUS_DDREN_REQ_MASK,
262 ~SPM_HWCG_DDREN_PWR_MB);
263 mmio_write_32(REG_PWR_STATUS_MSB_DDREN_REQ_MASK,
264 ~SPM_HWCG_DDREN_PWR_MSB_MB);
265 mmio_write_32(REG_MODULE_BUSY_DDREN_REQ_MASK,
266 ~SPM_HWCG_DDREN_MODULE_BUSY_MB);
267
268 /* HW CG for vrf18 resource req */
269 mmio_write_32(REG_PWR_STATUS_VRF18_REQ_MASK,
270 (uint32_t)(~SPM_HWCG_VRF18_PWR_MB));
271 mmio_write_32(REG_PWR_STATUS_MSB_VRF18_REQ_MASK,
272 (uint32_t)(~SPM_HWCG_VRF18_PWR_MSB_MB));
273 mmio_write_32(REG_MODULE_BUSY_VRF18_REQ_MASK,
274 (uint32_t)(~SPM_HWCG_VRF18_MODULE_BUSY_MB));
275
276 /* HW CG for infra resource req */
277 mmio_write_32(REG_PWR_STATUS_INFRA_REQ_MASK,
278 (uint32_t)(~SPM_HWCG_INFRA_PWR_MB));
279 mmio_write_32(REG_PWR_STATUS_MSB_INFRA_REQ_MASK,
280 (uint32_t)(~SPM_HWCG_INFRA_PWR_MSB_MB));
281 mmio_write_32(REG_MODULE_BUSY_INFRA_REQ_MASK,
282 (uint32_t)(~SPM_HWCG_INFRA_MODULE_BUSY_MB));
283
284 /* HW CG for pmic resource req */
285 mmio_write_32(REG_PWR_STATUS_PMIC_REQ_MASK,
286 (uint32_t)(~SPM_HWCG_PMIC_PWR_MB));
287 mmio_write_32(REG_PWR_STATUS_MSB_PMIC_REQ_MASK,
288 (uint32_t)(~SPM_HWCG_PMIC_PWR_MSB_MB));
289 mmio_write_32(REG_MODULE_BUSY_PMIC_REQ_MASK,
290 (uint32_t)(~SPM_HWCG_PMIC_MODULE_BUSY_MB));
291
292 /* HW CG for f26m resource req */
293 mmio_write_32(REG_PWR_STATUS_F26M_REQ_MASK,
294 (uint32_t)(~SPM_HWCG_F26M_PWR_MB));
295 mmio_write_32(REG_PWR_STATUS_MSB_F26M_REQ_MASK,
296 (uint32_t)(~SPM_HWCG_F26M_PWR_MSB_MB));
297 mmio_write_32(REG_MODULE_BUSY_F26M_REQ_MASK,
298 (uint32_t)(~SPM_HWCG_F26M_MODULE_BUSY_MB));
299
300 /* HW CG for vcore resource req */
301 mmio_write_32(REG_PWR_STATUS_VCORE_REQ_MASK,
302 (uint32_t)(~SPM_HWCG_VCORE_PWR_MB));
303 mmio_write_32(REG_PWR_STATUS_MSB_VCORE_REQ_MASK,
304 (uint32_t)(~SPM_HWCG_VCORE_PWR_MSB_MB));
305 mmio_write_32(REG_MODULE_BUSY_VCORE_REQ_MASK,
306 (uint32_t)(~SPM_HWCG_VCORE_MODULE_BUSY_MB));
307 }
308
309 #define PERI_CG(ofs) (PERICFG_AO_BASE + 0x10 + (0x4 * ofs))
310 #define PERI_REQ_DDREN_MB (BIT(PERI_REQ_EN_DMA) |\
311 BIT(PERI_REQ_EN_UART1) |\
312 BIT(PERI_REQ_EN_UART2) |\
313 BIT(PERI_REQ_EN_UART3) |\
314 BIT(PERI_REQ_EN_PWM) |\
315 BIT(PERI_REQ_EN_SPI0) |\
316 BIT(PERI_REQ_EN_SPI1) |\
317 BIT(PERI_REQ_EN_SPI2) |\
318 BIT(PERI_REQ_EN_SPI3) |\
319 BIT(PERI_REQ_EN_SPI4) |\
320 BIT(PERI_REQ_EN_SPI5) |\
321 BIT(PERI_REQ_EN_I2C) |\
322 BIT(PERI_REQ_EN_MSDC0) |\
323 BIT(PERI_REQ_EN_MSDC1) |\
324 BIT(PERI_REQ_EN_MSDC2) |\
325 BIT(PERI_REQ_EN_SSUSB0) |\
326 BIT(PERI_REQ_EN_SSUSB1) |\
327 BIT(PERI_REQ_EN_SSUSB2) |\
328 BIT(PERI_REQ_EN_SSUSB3) |\
329 BIT(PERI_REQ_EN_SSUSB4) |\
330 BIT(PERI_REQ_EN_PEXTP) |\
331 BIT(PERI_REQ_EN_AFE))
332
333 #define PERI_REQ_26M_MB (BIT(PERI_REQ_EN_DMA) |\
334 BIT(PERI_REQ_EN_UART1) |\
335 BIT(PERI_REQ_EN_UART2) |\
336 BIT(PERI_REQ_EN_UART3) |\
337 BIT(PERI_REQ_EN_PWM) |\
338 BIT(PERI_REQ_EN_SPI0) |\
339 BIT(PERI_REQ_EN_SPI1) |\
340 BIT(PERI_REQ_EN_SPI2) |\
341 BIT(PERI_REQ_EN_SPI3) |\
342 BIT(PERI_REQ_EN_SPI4) |\
343 BIT(PERI_REQ_EN_SPI5) |\
344 BIT(PERI_REQ_EN_I2C) |\
345 BIT(PERI_REQ_EN_MSDC0) |\
346 BIT(PERI_REQ_EN_MSDC1) |\
347 BIT(PERI_REQ_EN_MSDC2) |\
348 BIT(PERI_REQ_EN_SSUSB0) |\
349 BIT(PERI_REQ_EN_SSUSB1) |\
350 BIT(PERI_REQ_EN_SSUSB2) |\
351 BIT(PERI_REQ_EN_SSUSB4) |\
352 BIT(PERI_REQ_EN_PEXTP) |\
353 BIT(PERI_REQ_EN_AFE))
354
355 #define PERI_REQ_APSRC_MB (PERI_REQ_DDREN_MB)
356 #define PERI_REQ_EMI_MB (PERI_REQ_DDREN_MB)
357 #define PERI_REQ_INFRA_MB (PERI_REQ_DDREN_MB)
358 #define PERI_REQ_SYSPLL_MB (PERI_REQ_DDREN_MB)
359 #define PERI_REQ_PMIC_MB (PERI_REQ_DDREN_MB)
360 #define PERI_REQ_F26M_MB (PERI_REQ_26M_MB)
361
spm_peri_req_get_status(uint32_t idx,enum spm_peri_req_status type)362 uint32_t spm_peri_req_get_status(uint32_t idx, enum spm_peri_req_status type)
363 {
364 uint32_t val = 0, reg = 0;
365 struct spm_peri_req_info info;
366
367 switch (type) {
368 case PERI_RES_REQ_EN:
369
370 switch (idx) {
371 case PERI_REQ_DDREN:
372 DECLARE_PERI_REQ_STA_REG(PERI_REQ_DDREN, info);
373
374 break;
375 case PERI_REQ_APSRC:
376 DECLARE_PERI_REQ_STA_REG(PERI_REQ_APSRC, info);
377
378 break;
379 case PERI_REQ_EMI:
380 DECLARE_PERI_REQ_STA_REG(PERI_REQ_EMI, info);
381
382 break;
383 case PERI_REQ_SYSPLL:
384 DECLARE_PERI_REQ_STA_REG(PERI_REQ_SYSPLL, info);
385
386 break;
387 case PERI_REQ_INFRA:
388 DECLARE_PERI_REQ_STA_REG(PERI_REQ_INFRA, info);
389
390 break;
391 case PERI_REQ_PMIC:
392 DECLARE_PERI_REQ_STA_REG(PERI_REQ_PMIC, info);
393
394 break;
395 case PERI_REQ_F26M:
396 DECLARE_PERI_REQ_STA_REG(PERI_REQ_F26M, info);
397
398 break;
399 default:
400 PERI_REQ_STA_INFO_INIT(info);
401 break;
402 }
403
404 if (!info.req_sta)
405 return 0;
406
407 reg = info.req_sta;
408 val = (mmio_read_32(reg) & PERI_REQ_EN_MASK);
409
410 break;
411 default:
412 break;
413 }
414 return val;
415 }
416
spm_peri_req_name(uint32_t idex,char * name,size_t sz)417 int spm_peri_req_name(uint32_t idex, char *name, size_t sz)
418 {
419 int ret = 0;
420
421 if (!name)
422 return -1;
423
424 switch (idex) {
425 case PERI_REQ_DDREN:
426 ret = snprintf(name, sz - 1, "ddren");
427 break;
428 case PERI_REQ_APSRC:
429 ret = snprintf(name, sz - 1, "apsrc");
430 break;
431 case PERI_REQ_EMI:
432 ret = snprintf(name, sz - 1, "emi");
433 break;
434 case PERI_REQ_SYSPLL:
435 ret = snprintf(name, sz - 1, "syspll");
436 break;
437 case PERI_REQ_INFRA:
438 ret = snprintf(name, sz - 1, "infra");
439 break;
440 case PERI_REQ_PMIC:
441 ret = snprintf(name, sz - 1, "pmic");
442 break;
443 case PERI_REQ_F26M:
444 ret = snprintf(name, sz - 1, "26m_vcore");
445 break;
446 default:
447 ret = -1;
448 break;
449 }
450
451 name[sz - 1] = '\0';
452
453 return ret;
454 }
455
spm_peri_req_get_status_raw(enum spm_peri_req_status_raw type,uint32_t idx,char * name,size_t sz)456 uint32_t spm_peri_req_get_status_raw(enum spm_peri_req_status_raw type,
457 uint32_t idx, char *name, size_t sz)
458 {
459 return 0;
460 }
461
spm_peri_req_get_default(uint32_t res)462 static uint32_t spm_peri_req_get_default(uint32_t res)
463 {
464 struct spm_peri_req_info info;
465
466 if (res & MT_SPM_DRAM_S1)
467 DECLARE_PERI_REQ_DEFAULT(DDREN, info);
468 else if (res & MT_SPM_DRAM_S0)
469 DECLARE_PERI_REQ_DEFAULT(APSRC, info);
470 else if (res & MT_SPM_EMI)
471 DECLARE_PERI_REQ_DEFAULT(EMI, info);
472 else if (res & MT_SPM_SYSPLL)
473 DECLARE_PERI_REQ_DEFAULT(SYSPLL, info);
474 else if (res & MT_SPM_INFRA)
475 DECLARE_PERI_REQ_DEFAULT(INFRA, info);
476 else if (res & MT_SPM_PMIC)
477 DECLARE_PERI_REQ_DEFAULT(PMIC, info);
478 else if (res & (MT_SPM_26M | MT_SPM_VCORE))
479 DECLARE_PERI_REQ_DEFAULT(F26M, info);
480 else
481 PERI_REQ_EN_INFO_INIT(info);
482
483 return info.req_en;
484 }
485
spm_peri_req_mask_get(uint32_t res)486 static uint32_t spm_peri_req_mask_get(uint32_t res)
487 {
488 struct spm_peri_req_info info;
489 uint32_t raw_val = 0, reg = 0;
490
491 if (res & MT_SPM_DRAM_S1)
492 DECLARE_PERI_REQ_EN_REG(PERI_REQ_DDREN, info);
493 else if (res & MT_SPM_DRAM_S0)
494 DECLARE_PERI_REQ_EN_REG(PERI_REQ_APSRC, info);
495 else if (res & MT_SPM_EMI)
496 DECLARE_PERI_REQ_EN_REG(PERI_REQ_EMI, info);
497 else if (res & MT_SPM_SYSPLL)
498 DECLARE_PERI_REQ_EN_REG(PERI_REQ_SYSPLL, info);
499 else if (res & MT_SPM_INFRA)
500 DECLARE_PERI_REQ_EN_REG(PERI_REQ_INFRA, info);
501 else if (res & MT_SPM_PMIC)
502 DECLARE_PERI_REQ_EN_REG(PERI_REQ_PMIC, info);
503 else if (res & (MT_SPM_26M | MT_SPM_VCORE))
504 DECLARE_PERI_REQ_EN_REG(PERI_REQ_F26M, info);
505 else
506 PERI_REQ_EN_INFO_INIT(info);
507
508 if (!info.req_en)
509 return 0;
510
511 reg = info.req_en;
512
513 raw_val = (mmio_read_32(reg) & PERI_REQ_EN_MASK);
514
515 return raw_val;
516 }
517
spm_peri_req_get_setting(uint32_t res,enum spm_peri_req_sta_type sta_type,struct spm_peri_req_sta * sta)518 int spm_peri_req_get_setting(uint32_t res, enum spm_peri_req_sta_type sta_type,
519 struct spm_peri_req_sta *sta)
520 {
521 int ret = 0;
522
523 if (!sta)
524 return -1;
525
526 switch (sta_type) {
527 case PERI_REQ_STA_DEFAULT_MASK:
528 sta->sta = spm_peri_req_get_default(res);
529 break;
530 case PERI_REQ_STA_MASK:
531 sta->sta = spm_peri_req_mask_get(res);
532 break;
533 default:
534 ret = -1;
535 MT_SPM_HW_CG_STA_INIT(sta);
536 break;
537 }
538 return ret;
539 }
540
spm_peri_req_index2res(uint32_t idx)541 static uint32_t spm_peri_req_index2res(uint32_t idx)
542 {
543 uint32_t res;
544
545 if (idx >= PERI_REQ_MAX)
546 return 0;
547
548 switch (idx) {
549 case PERI_REQ_DDREN:
550 res = MT_SPM_DRAM_S1;
551 break;
552 case PERI_REQ_APSRC:
553 res = MT_SPM_DRAM_S0;
554 break;
555 case PERI_REQ_EMI:
556 res = MT_SPM_EMI;
557 break;
558 case PERI_REQ_SYSPLL:
559 res = MT_SPM_SYSPLL;
560 break;
561 case PERI_REQ_INFRA:
562 res = MT_SPM_INFRA;
563 break;
564 case PERI_REQ_PMIC:
565 res = (MT_SPM_PMIC);
566 break;
567 case PERI_REQ_F26M:
568 res = (MT_SPM_26M | MT_SPM_VCORE);
569 break;
570 default:
571 res = 0;
572 }
573 return res;
574 }
575
spm_peri_req_get_setting_by_index(uint32_t idx,enum spm_peri_req_sta_type sta_type,struct spm_peri_req_sta * sta)576 int spm_peri_req_get_setting_by_index(uint32_t idx,
577 enum spm_peri_req_sta_type sta_type,
578 struct spm_peri_req_sta *sta)
579 {
580 uint32_t res = spm_peri_req_index2res(idx);
581
582 return spm_peri_req_get_setting(res, sta_type, sta);
583 }
584
__spm_peri_req_ctrl(struct spm_peri_req_info * info,uint32_t is_set,uint32_t val)585 static void __spm_peri_req_ctrl(struct spm_peri_req_info *info, uint32_t is_set,
586 uint32_t val)
587 {
588 uint32_t reg;
589
590 if (!info)
591 return;
592
593 reg = info->req_en;
594
595 if (!reg)
596 return;
597
598 if (is_set)
599 mmio_setbits_32(reg, val);
600 else
601 mmio_clrbits_32(reg, val);
602 }
603
spm_peri_req_ctrl(uint32_t res,uint32_t is_set,uint32_t val)604 void spm_peri_req_ctrl(uint32_t res, uint32_t is_set, uint32_t val)
605 {
606 struct spm_peri_req_info info;
607
608 if (res & MT_SPM_DRAM_S1)
609 DECLARE_PERI_REQ_EN_REG(PERI_REQ_DDREN, info);
610 else if (res & MT_SPM_DRAM_S0)
611 DECLARE_PERI_REQ_EN_REG(PERI_REQ_APSRC, info);
612 else if (res & MT_SPM_EMI)
613 DECLARE_PERI_REQ_EN_REG(PERI_REQ_EMI, info);
614 else if (res & MT_SPM_SYSPLL)
615 DECLARE_PERI_REQ_EN_REG(PERI_REQ_SYSPLL, info);
616 else if (res & MT_SPM_INFRA)
617 DECLARE_PERI_REQ_EN_REG(PERI_REQ_INFRA, info);
618 else if (res & MT_SPM_PMIC)
619 DECLARE_PERI_REQ_EN_REG(MT_SPM_PMIC, info);
620 else if (res & (MT_SPM_26M | MT_SPM_VCORE))
621 DECLARE_PERI_REQ_EN_REG(PERI_REQ_F26M, info);
622 else
623 PERI_REQ_EN_INFO_INIT(info);
624
625 if (info.req_en)
626 __spm_peri_req_ctrl(&info, is_set, val);
627 }
628
spm_peri_req_ctrl_by_index(uint32_t idx,uint32_t is_set,uint32_t val)629 void spm_peri_req_ctrl_by_index(uint32_t idx, uint32_t is_set, uint32_t val)
630 {
631 uint32_t res = spm_peri_req_index2res(idx);
632
633 if (res)
634 spm_peri_req_ctrl(res, is_set, val);
635 }
636
spm_peri_req_init(void)637 static void spm_peri_req_init(void)
638 {
639 mmio_write_32(REG_PERI_REQ_EN(PERI_REQ_DDREN), PERI_REQ_DDREN_MB);
640
641 mmio_write_32(REG_PERI_REQ_EN(PERI_REQ_EMI), PERI_REQ_EMI_MB);
642
643 mmio_write_32(REG_PERI_REQ_EN(PERI_REQ_APSRC), PERI_REQ_APSRC_MB);
644
645 mmio_write_32(REG_PERI_REQ_EN(PERI_REQ_INFRA), PERI_REQ_INFRA_MB);
646
647 mmio_write_32(REG_PERI_REQ_EN(PERI_REQ_SYSPLL), PERI_REQ_SYSPLL_MB);
648
649 mmio_write_32(REG_PERI_REQ_EN(PERI_REQ_PMIC), PERI_REQ_PMIC_MB);
650
651 mmio_write_32(REG_PERI_REQ_EN(PERI_REQ_F26M), PERI_REQ_F26M_MB);
652 }
653
spm_hwreq_init(void)654 void spm_hwreq_init(void)
655 {
656 spm_infra_swcg_init();
657 spm_hwcg_init();
658 spm_peri_req_init();
659 }
660