Merge "feat(versal2): add SPMD support for SPMC at S-EL1" into integration

feat(el3-spmc): parse and report VM availability messages

Parse vm-availability-messages from the SP manifest
and report them with FFA_PARTITION_INFO_GET.

Change-Id: I3494959527644795a1a729ff3cb505

feat(el3-spmc): parse and report VM availability messages

Parse vm-availability-messages from the SP manifest
and report them with FFA_PARTITION_INFO_GET.

Change-Id: I3494959527644795a1a729ff3cb505aab1ba9e8c
Signed-off-by: Andrei Homescu <ahomescu@google.com>

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Merge "fix(smccc): cleanup unused declaration" into integration

Merge changes from topic "xl/separate-bl2" into integration

* changes:
feat(fwu): documentation for BL2 separation
feat(fwu): separate bl2 image from rest of the FIP
feat(fwu): create flag for

Merge changes from topic "xl/separate-bl2" into integration

* changes:
feat(fwu): documentation for BL2 separation
feat(fwu): separate bl2 image from rest of the FIP
feat(fwu): create flag for BL2 separation

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feat(fwu): documentation for BL2 separation

The separation of BL2 introduce a new flag in the build
option, SEPARATE_BL2_FIP.

Change-Id: I64e231d40376c39112bce66851af9ccb37d37382
Signed-off-by: Xia

feat(fwu): documentation for BL2 separation

The separation of BL2 introduce a new flag in the build
option, SEPARATE_BL2_FIP.

Change-Id: I64e231d40376c39112bce66851af9ccb37d37382
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(smccc): cleanup unused declaration

Remove check_wa_cve_2024_7881() declaration left behind by patch
fd04156eb792963cb21144063e421d074efa6386.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakas

fix(smccc): cleanup unused declaration

Remove check_wa_cve_2024_7881() declaration left behind by patch
fd04156eb792963cb21144063e421d074efa6386.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Iae81e0bcbd2feb2b72a4e4e8fd27a27ae00c9cb4

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Merge "feat(arm): unify Linux kernel as BL33 handling" into integration

feat(arm): unify Linux kernel as BL33 handling

Streamlines and unifies how Arm platforms pass arguments to the Linux
kernel when it is loaded as BL33. It replaces the FVP specific macro
`FVP_HW_CONF

feat(arm): unify Linux kernel as BL33 handling

Streamlines and unifies how Arm platforms pass arguments to the Linux
kernel when it is loaded as BL33. It replaces the FVP specific macro
`FVP_HW_CONFIG_ADDR` with a common macro `ARM_HW_CONFIG_ADDR` for
accessing the device tree blob base address.

For FVP the DT address is set to use `ARM_PRELOADED_DTB_BASE` if
provided, falling back to a default address otherwise.

This provides a consistent mechanism for Arm platforms to define and
override the DTB base address used during kernel handoff. It reduces the
chance of misconfiguration, and simplifies platform integration.

Change-Id: Ib668dbb1de9d42cf41c0b0ee9a316f054891752a
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(fwu): separate bl2 image from rest of the FIP

Create a separate partition for BL2 image in the GPT.
Modify the makefile to package BL2 image and its certificates
into a different FIP image.

Ch

feat(fwu): separate bl2 image from rest of the FIP

Create a separate partition for BL2 image in the GPT.
Modify the makefile to package BL2 image and its certificates
into a different FIP image.

Change-Id: I950883ea0c393a2a063ad9e51bb963cbac742705
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge "fix(ti): specify allowable rcv_addr in mailbox" into integration

Merge "feat(smccc): enable support for FEAT_MEC" into integration

Merge "chore(dev-deps): bump the dev-deps group across 1 directory with 3 updates" into integration

Merge "feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support" into integration

fix(gpt): fix fill_l1_cont_desc() function

GPT library function fill_l1_cont_desc() writes
contiguous descriptors and is called in a loop
by fill_l1_tbl() which fills out GPI entries in
in a single

fix(gpt): fix fill_l1_cont_desc() function

GPT library function fill_l1_cont_desc() writes
contiguous descriptors and is called in a loop
by fill_l1_tbl() which fills out GPI entries in
in a single L1 table. The loop terminates when
the address of the first granule in range 'first'
exceeds address of the last granule (inclusive)
'last'.
This patch fixes the issue when fill_l1_cont_desc()
was iterating through all matching contiguous block
sizes 512, 32 and 2MB in a loop and filling consecutive
smaller descriptors instead of filling a single one with
a maximum size. This resulted for memory region 0x80000000
of size 1.5GB (3*512MB)to be filled with 2 512MB, 8 32MB and
128 2MB contiguous descriptors instead of 3 512MB descriptors
with build option RME_GPT_MAX_BLOCK=512.
This patch also removes unused definition of ARM_PAS_GPI_ANY
macro in fvp_pas_def.h.

Change-Id: I9fcff512af306a57d17dee0bade74d2f3f79b5e9
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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feat(smccc): enable support for FEAT_MEC

Add SCR_EL3.FEAT_MEC bit to the SMCCC_ARCH_FEATURE_AVAILABILITY
bitmask to allow RMM to query MEC support.

Change-Id: I2c2130fc4d61eb1a14124931c88e323c82be7

feat(smccc): enable support for FEAT_MEC

Add SCR_EL3.FEAT_MEC bit to the SMCCC_ARCH_FEATURE_AVAILABILITY
bitmask to allow RMM to query MEC support.

Change-Id: I2c2130fc4d61eb1a14124931c88e323c82be7924
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>

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Merge "docs(maintainers): add myself as code owner for the GICv5 driver" into integration

Merge "fix(neoverse-rd): add console initialisation to BL31" into integration

fix(imx8mp): assign wdog1 to domain0 only

Normally, wdog1 is used by A53 side, and it should be stopped when
A53 domain enters STOP mode. After Power-on-Reset this watchdog is owned
by both M7 & A53

fix(imx8mp): assign wdog1 to domain0 only

Normally, wdog1 is used by A53 side, and it should be stopped when
A53 domain enters STOP mode. After Power-on-Reset this watchdog is owned
by both M7 & A53 side. This watchdog can only enter STOP mode only when
both A53 & M7 enter STOP mode. This is not reasonable as this watchdog
is only used by A53 side, so assign wdog1 to domain0(a53 side) only.

Change-Id: I4c04a8c7f3cba4713f410866c18fef88fcbe9f11
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>

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Merge "fix(st-clock): add ck_bus_risaf4 clock for STM32MP2" into integration

Merge changes Id38d6f1b,I5fcfe8dd,I7f3b50e5 into integration

* changes:
fix(cpus): inform the compiler that struct cpu_ops is aligned
refactor(el3-runtime): move the initialisation of the cpu_op

Merge changes Id38d6f1b,I5fcfe8dd,I7f3b50e5 into integration

* changes:
fix(cpus): inform the compiler that struct cpu_ops is aligned
refactor(el3-runtime): move the initialisation of the cpu_ops_ptr to C
fix(aarch32): make get_cpu_ops_ptr() PCS compliant

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chore(dev-deps): bump the dev-deps group across 1 directory with 3 updates

Bumps the dev-deps group with 3 updates in the / directory: [@commitlint/cli](https://github.com/conventional-changelog/com

chore(dev-deps): bump the dev-deps group across 1 directory with 3 updates

Bumps the dev-deps group with 3 updates in the / directory: [@commitlint/cli](https://github.com/conventional-changelog/commitlint/tree/HEAD/@commitlint/cli), [@commitlint/config-conventional](https://github.com/conventional-changelog/commitlint/tree/HEAD/@commitlint/config-conventional) and [@commitlint/cz-commitlint](https://github.com/conventional-changelog/commitlint/tree/HEAD/@commitlint/cz-commitlint).


Updates `@commitlint/cli` from 19.8.0 to 19.8.1
- [Release notes](https://github.com/conventional-changelog/commitlint/releases)
- [Changelog](https://github.com/conventional-changelog/commitlint/blob/master/@commitlint/cli/CHANGELOG.md)
- [Commits](https://github.com/conventional-changelog/commitlint/commits/v19.8.1/@commitlint/cli)

Updates `@commitlint/config-conventional` from 19.8.0 to 19.8.1
- [Release notes](https://github.com/conventional-changelog/commitlint/releases)
- [Changelog](https://github.com/conventional-changelog/commitlint/blob/master/@commitlint/config-conventional/CHANGELOG.md)
- [Commits](https://github.com/conventional-changelog/commitlint/commits/v19.8.1/@commitlint/config-conventional)

Updates `@commitlint/cz-commitlint` from 19.8.0 to 19.8.1
- [Release notes](https://github.com/conventional-changelog/commitlint/releases)
- [Changelog](https://github.com/conventional-changelog/commitlint/blob/master/@commitlint/cz-commitlint/CHANGELOG.md)
- [Commits](https://github.com/conventional-changelog/commitlint/commits/v19.8.1/@commitlint/cz-commitlint)

...
updated-dependencies:
- dependency-name: "@commitlint/cli"
dependency-version: 19.8.1
dependency-type: direct:development
update-type: version-update:semver-patch
dependency-group: dev-deps
- dependency-name: "@commitlint/config-conventional"
dependency-version: 19.8.1
dependency-type: direct:development
update-type: version-update:semver-patch
dependency-group: dev-deps
- dependency-name: "@commitlint/cz-commitlint"
dependency-version: 19.8.1
dependency-type: direct:development
update-type: version-update:semver-patch
dependency-group: dev-deps
...

Signed-off-by: dependabot[bot] <support@github.com>
Change-Id: Iea28f4da58a5e27abb5a9d7ee4be4e9ae67a82a2

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chore(versal2): rename versal2 to Versal Gen 2

The term Versal2 should be updated to Versal Gen 2.

Change-Id: Iac94ef32604f88ec030bf95ec35484b72a0f7ffa
Signed-off-by: Prasad Kummari <prasad.kummari

chore(versal2): rename versal2 to Versal Gen 2

The term Versal2 should be updated to Versal Gen 2.

Change-Id: Iac94ef32604f88ec030bf95ec35484b72a0f7ffa
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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Merge "feat(cpus): add support for Canyon CPU" into integration

Merge "fix(arm): increase reserved DRAM1 mem for NS images" into integration

feat(versal2): add SPMD support for SPMC at S-EL1

Added support for SPMD when SPMC is running at S-EL1 on Versal Gen 2
platform. Added DTB with manifest addresses to BL32 for proper
initialization.

feat(versal2): add SPMD support for SPMC at S-EL1

Added support for SPMD when SPMC is running at S-EL1 on Versal Gen 2
platform. Added DTB with manifest addresses to BL32 for proper
initialization. Added `plat_spmd_handle_group0_interrupt` to handle
Group0 interrupts in SPMD. Added a new manifest source file compliant
with FFA 1.0 specification in which load_address and entrypoint
points to BL32 base address.

Change-Id: I518e2e799d3b86fcd67f9fee0af42503ca705488
Signed-off-by: Pranav Tilak <pranav.vinaytilak@amd.com>

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