1 /* 2 * Copyright 2020-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <context.h> 14 #include <drivers/arm/tzc380.h> 15 #include <drivers/console.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <lib/el3_runtime/context_mgmt.h> 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 #include <plat/common/platform.h> 21 22 #include <dram.h> 23 #include <gpc.h> 24 #include <imx_aipstz.h> 25 #include <imx_uart.h> 26 #include <imx_rdc.h> 27 #include <imx8m_caam.h> 28 #include <imx8m_ccm.h> 29 #include <imx8m_csu.h> 30 #include <imx8m_snvs.h> 31 #include <platform_def.h> 32 #include <plat_common.h> 33 #include <plat_imx8.h> 34 35 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 36 37 static const mmap_region_t imx_mmap[] = { 38 GIC_MAP, AIPS_MAP, OCRAM_S_MAP, DDRC_MAP, 39 NOC_MAP, CAAM_RAM_MAP, NS_OCRAM_MAP, 40 ROM_MAP, DRAM_MAP, 41 {0}, 42 }; 43 44 static const struct aipstz_cfg aipstz[] = { 45 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 46 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 47 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 48 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 49 {0}, 50 }; 51 52 static struct imx_rdc_cfg rdc[] = { 53 /* Master domain assignment */ 54 RDC_MDAn(RDC_MDA_M7, DID1), 55 56 /* peripherals domain permission */ 57 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), 58 RDC_PDAPn(RDC_PDAP_WDOG1, D0R | D0W), 59 60 /* memory region */ 61 62 /* Sentinel */ 63 {0}, 64 }; 65 66 static const struct imx_csu_cfg csu_cfg[] = { 67 /* peripherals csl setting */ 68 CSU_CSLx(CSU_CSL_OCRAM, CSU_SEC_LEVEL_2, LOCKED), 69 CSU_CSLx(CSU_CSL_OCRAM_S, CSU_SEC_LEVEL_2, LOCKED), 70 CSU_CSLx(CSU_CSL_RDC, CSU_SEC_LEVEL_3, LOCKED), 71 CSU_CSLx(CSU_CSL_TZASC, CSU_SEC_LEVEL_5, LOCKED), 72 CSU_CSLx(CSU_CSL_CSU, CSU_SEC_LEVEL_5, LOCKED), 73 74 /* master HP0~1 */ 75 76 /* SA setting */ 77 CSU_SA(CSU_SA_M7, NON_SEC_ACCESS, LOCKED), 78 CSU_SA(CSU_SA_SDMA1, NON_SEC_ACCESS, LOCKED), 79 CSU_SA(CSU_SA_PCIE_CTRL1, NON_SEC_ACCESS, LOCKED), 80 CSU_SA(CSU_SA_USB1, NON_SEC_ACCESS, LOCKED), 81 CSU_SA(CSU_SA_USB2, NON_SEC_ACCESS, LOCKED), 82 CSU_SA(CSU_SA_APB_HDMA, NON_SEC_ACCESS, LOCKED), 83 CSU_SA(CSU_SA_ENET1, NON_SEC_ACCESS, LOCKED), 84 CSU_SA(CSU_SA_USDHC1, NON_SEC_ACCESS, LOCKED), 85 CSU_SA(CSU_SA_USDHC2, NON_SEC_ACCESS, LOCKED), 86 CSU_SA(CSU_SA_USDHC3, NON_SEC_ACCESS, LOCKED), 87 CSU_SA(CSU_SA_HUGO, NON_SEC_ACCESS, LOCKED), 88 CSU_SA(CSU_SA_DAP, NON_SEC_ACCESS, LOCKED), 89 CSU_SA(CSU_SA_SDMA2, NON_SEC_ACCESS, LOCKED), 90 CSU_SA(CSU_SA_SDMA3, NON_SEC_ACCESS, LOCKED), 91 CSU_SA(CSU_SA_LCDIF1, NON_SEC_ACCESS, LOCKED), 92 CSU_SA(CSU_SA_ISI, NON_SEC_ACCESS, LOCKED), 93 CSU_SA(CSU_SA_NPU, NON_SEC_ACCESS, LOCKED), 94 CSU_SA(CSU_SA_LCDIF2, NON_SEC_ACCESS, LOCKED), 95 CSU_SA(CSU_SA_HDMI_TX, NON_SEC_ACCESS, LOCKED), 96 CSU_SA(CSU_SA_ENET2, NON_SEC_ACCESS, LOCKED), 97 CSU_SA(CSU_SA_GPU3D, NON_SEC_ACCESS, LOCKED), 98 CSU_SA(CSU_SA_GPU2D, NON_SEC_ACCESS, LOCKED), 99 CSU_SA(CSU_SA_VPU_G1, NON_SEC_ACCESS, LOCKED), 100 CSU_SA(CSU_SA_VPU_G2, NON_SEC_ACCESS, LOCKED), 101 CSU_SA(CSU_SA_VPU_VC8000E, NON_SEC_ACCESS, LOCKED), 102 CSU_SA(CSU_SA_AUDIO_EDMA, NON_SEC_ACCESS, LOCKED), 103 CSU_SA(CSU_SA_ISP1, NON_SEC_ACCESS, LOCKED), 104 CSU_SA(CSU_SA_ISP2, NON_SEC_ACCESS, LOCKED), 105 CSU_SA(CSU_SA_DEWARP, NON_SEC_ACCESS, LOCKED), 106 CSU_SA(CSU_SA_GIC500, NON_SEC_ACCESS, LOCKED), 107 108 /* HP control setting */ 109 110 /* Sentinel */ 111 {0} 112 }; 113 114 static entry_point_info_t bl32_image_ep_info; 115 static entry_point_info_t bl33_image_ep_info; 116 117 /* get SPSR for BL33 entry */ 118 static uint32_t get_spsr_for_bl33_entry(void) 119 { 120 unsigned long el_status; 121 unsigned long mode; 122 uint32_t spsr; 123 124 /* figure out what mode we enter the non-secure world */ 125 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 126 el_status &= ID_AA64PFR0_ELX_MASK; 127 128 mode = (el_status) ? MODE_EL2 : MODE_EL1; 129 130 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 131 return spsr; 132 } 133 134 static void bl31_tzc380_setup(void) 135 { 136 unsigned int val; 137 138 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); 139 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 140 return; 141 142 tzc380_init(IMX_TZASC_BASE); 143 144 /* 145 * Need to substact offset 0x40000000 from CPU address when 146 * programming tzasc region for i.mx8mp. 147 */ 148 149 /* Enable 1G-5G S/NS RW */ 150 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 151 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 152 } 153 154 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 155 u_register_t arg2, u_register_t arg3) 156 { 157 unsigned int console_base = IMX_BOOT_UART_BASE; 158 static console_t console; 159 unsigned int val; 160 unsigned int i; 161 int ret; 162 163 /* Enable CSU NS access permission */ 164 for (i = 0; i < 64; i++) { 165 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 166 } 167 168 imx_aipstz_init(aipstz); 169 170 if (console_base == 0U) { 171 console_base = imx8m_uart_get_base(); 172 } 173 174 imx_rdc_init(rdc, console_base); 175 176 imx_csu_init(csu_cfg); 177 178 /* config the ocram memory range for secure access */ 179 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, 0x4E1); 180 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c); 181 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000); 182 183 console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ, 184 IMX_CONSOLE_BAUDRATE, &console); 185 /* This console is only used for boot stage */ 186 console_set_scope(&console, CONSOLE_FLAG_BOOT); 187 188 imx8m_caam_init(); 189 190 /* 191 * tell BL3-1 where the non-secure software image is located 192 * and the entry state information. 193 */ 194 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 195 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 196 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 197 198 #if defined(SPD_opteed) || defined(SPD_trusty) 199 /* Populate entry point information for BL32 */ 200 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 201 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 202 bl32_image_ep_info.pc = BL32_BASE; 203 bl32_image_ep_info.spsr = 0; 204 205 /* Pass TEE base and size to bl33 */ 206 bl33_image_ep_info.args.arg1 = BL32_BASE; 207 bl33_image_ep_info.args.arg2 = BL32_SIZE; 208 209 #ifdef SPD_trusty 210 bl32_image_ep_info.args.arg0 = BL32_SIZE; 211 bl32_image_ep_info.args.arg1 = BL32_BASE; 212 #else 213 /* Make sure memory is clean */ 214 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); 215 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 216 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 217 #endif 218 #endif 219 ret = imx_bl31_params_parse(arg0, IMX_NS_OCRAM_SIZE, IMX_NS_OCRAM_BASE, 220 &bl32_image_ep_info, &bl33_image_ep_info); 221 if (ret != 0) { 222 ret = imx_bl31_params_parse(arg0, IMX_TCM_BASE, IMX_TCM_SIZE, 223 &bl32_image_ep_info, 224 &bl33_image_ep_info); 225 } 226 227 #if !defined(SPD_opteed) && !defined(SPD_trusty) 228 enable_snvs_privileged_access(); 229 #endif 230 231 bl31_tzc380_setup(); 232 } 233 234 #define MAP_BL31_TOTAL \ 235 MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE) 236 #define MAP_BL31_RO \ 237 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE) 238 #define MAP_COHERENT_MEM \ 239 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ 240 MT_DEVICE | MT_RW | MT_SECURE) 241 #define MAP_BL32_TOTAL \ 242 MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW) 243 244 void bl31_plat_arch_setup(void) 245 { 246 const mmap_region_t bl_regions[] = { 247 MAP_BL31_TOTAL, 248 MAP_BL31_RO, 249 #if USE_COHERENT_MEM 250 MAP_COHERENT_MEM, 251 #endif 252 #if defined(SPD_opteed) || defined(SPD_trusty) 253 /* Map TEE memory */ 254 MAP_BL32_TOTAL, 255 #endif 256 {0} 257 }; 258 259 setup_page_tables(bl_regions, imx_mmap); 260 enable_mmu_el3(0); 261 } 262 263 void bl31_platform_setup(void) 264 { 265 generic_delay_timer_init(); 266 267 /* select the CKIL source to 32K OSC */ 268 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 269 270 /* Init the dram info */ 271 dram_info_init(SAVED_DRAM_TIMING_BASE); 272 273 plat_gic_driver_init(); 274 plat_gic_init(); 275 276 imx_gpc_init(); 277 } 278 279 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 280 { 281 if (type == NON_SECURE) { 282 return &bl33_image_ep_info; 283 } 284 285 if (type == SECURE) { 286 return &bl32_image_ep_info; 287 } 288 289 return NULL; 290 } 291 292 unsigned int plat_get_syscnt_freq2(void) 293 { 294 return COUNTER_FREQUENCY; 295 } 296 297 #ifdef SPD_trusty 298 void plat_trusty_set_boot_args(aapcs64_params_t *args) 299 { 300 args->arg0 = BL32_SIZE; 301 args->arg1 = BL32_BASE; 302 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 303 } 304 #endif 305