plat/qemu_sbsa: Remove cortex_a53 and aem_generic

The qemu_sbsa platform uses 42bit address size but
the cortex-a53 only supports 40bit addressing, the
cpu is incompatible with the platform.

The ae

plat/qemu_sbsa: Remove cortex_a53 and aem_generic

The qemu_sbsa platform uses 42bit address size but
the cortex-a53 only supports 40bit addressing, the
cpu is incompatible with the platform.

The aem_generic is also not used with qemu_sbsa, in
fact, the platform currently only properly supports
the cortex-a57 cpu.

Change-Id: I91c92533116f1c3451d01ca99824e91d3d58df14
Signed-off-by: Tomas Pilar <tomas@nuviateam.com>

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plat: marvell: armada: Building ${DOIMAGETOOL} is only for a8k

Currently a3k target is misusing ${DOIMAGETOOL} target for building flash
and UART images. It is not used for building image tool.

So

plat: marvell: armada: Building ${DOIMAGETOOL} is only for a8k

Currently a3k target is misusing ${DOIMAGETOOL} target for building flash
and UART images. It is not used for building image tool.

So move ${DOIMAGETOOL} target from common marvell include file into a8k
include file and add correct invocation of ${MAKE} into a3k for building
flash and UART images.

Part of this change is also checks that MV_DDR_PATH for a3k was specified
by user as this option is required for building a3k flash and UART images.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I5ae9d08b8505460933f17836c9b6435fd6e51bb6

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mediatek: mt8183: add timer V20 compensation

add timer driver.

Signed-off-by: Fengquan Chen <fengquan.chen@mediatek.com>
Change-Id: I60a7273f922233a618a6163b802c0858ed89f75f

Merge "docs: code review guidelines" into integration

Use preallocated parts of the HASH struct

When OpenSSL's macro allocates the HASH struct, it allocates the fields
as well. After this allocation, the prior code would assign over the
pointers inside

Use preallocated parts of the HASH struct

When OpenSSL's macro allocates the HASH struct, it allocates the fields
as well. After this allocation, the prior code would assign over the
pointers inside the HASH struct, leaking these fields. This patch
avoids allocating extra copies of these members.

Change-Id: I50a38b0a04b52ec54d6388db0f694feb578d2818
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

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Free arguments copied with strdup

Change-Id: I0ad9620145c2a9c4450b9bf20cd1f70c9db6593c
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

Free keys after use

Change-Id: I16ba4420ffeb9aa439e0a09a1b34d2aba2e1eb6e
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

Free X509_EXTENSIONs

Previously, we would leak these extensions as they are not freed by the
stack. An except from the `sk_TYPE_free` documentation:

sk_TYPE_free() frees up the sk structure. It

Free X509_EXTENSIONs

Previously, we would leak these extensions as they are not freed by the
stack. An except from the `sk_TYPE_free` documentation:

sk_TYPE_free() frees up the sk structure. It does not free up any
elements of sk. After this call sk is no longer valid.

The fix is to drain the stack and free its elements before freeing the
stack. sk_TYPE_pop_free does this, so we use that instead.

Change-Id: Ie70c302f9dda5af1a7243f163d36e99916ee639c
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

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plat: tc0: Configure TZC with secure world regions

This includes configuration for SPMC and trusted OS.

Change-Id: Ie24df200f446b3f5b23f5f764b115c7191e6ada3
Signed-off-by: Usama Arif <usama.arif@ar

plat: tc0: Configure TZC with secure world regions

This includes configuration for SPMC and trusted OS.

Change-Id: Ie24df200f446b3f5b23f5f764b115c7191e6ada3
Signed-off-by: Usama Arif <usama.arif@arm.com>
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>

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plat: tc0: Enable SPMC execution at S-EL2

This patch enables SPMC execution at S-EL2 by adding below changes

- Map TC0_MAP_TZC_DRAM1 for loading SPMC
- Add details of cactus test secure par

plat: tc0: Enable SPMC execution at S-EL2

This patch enables SPMC execution at S-EL2 by adding below changes

- Map TC0_MAP_TZC_DRAM1 for loading SPMC
- Add details of cactus test secure partitions
- Adds tc0 spmc manifest file with details on secure partitions
- Inlcude TOS_FW_CONFIG when SPM is spmd
- Increases bl2 image size

SPMC at S-EL2 is only enabled when build with SPD=spmd.

Change-Id: I4c5f70911903c232ee8ecca57f1e288d6b1cd647
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>

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plat: tc0: Add TZC DRAM1 region for SPMC and trusted OS

- Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for TC0_TZC_DRAM1
- Add TC0_NS_DRAM1 base and mapping
- Reserve memory region in tc0.dts

Change-Id

plat: tc0: Add TZC DRAM1 region for SPMC and trusted OS

- Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for TC0_TZC_DRAM1
- Add TC0_NS_DRAM1 base and mapping
- Reserve memory region in tc0.dts

Change-Id: If2431f7f68e4255e28c86a0e89637dab7c424a13
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>

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plat: arm: Make BL32_BASE platform dependent when SPD_spmd is enabled

To support platforms without Trusted DRAM this patch defines
PLAT_ARM_SPMC_BASE and enables platform to use either Trusted DRAM

plat: arm: Make BL32_BASE platform dependent when SPD_spmd is enabled

To support platforms without Trusted DRAM this patch defines
PLAT_ARM_SPMC_BASE and enables platform to use either Trusted DRAM or
DRAM region behind TZC.

Change-Id: Icaa5c7d33334258ff27e8e0bfd0812c304e68ae4
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>

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plat: tc0: Disable SPE

Statistical Profiling Extension is not supported by Matterhorn core

Change-Id: Iec652f1c6d6b6a9bf118ba682276a7c70a6abc0d
Signed-off-by: Arunachalam Ganapathy <arunachalam.gan

plat: tc0: Disable SPE

Statistical Profiling Extension is not supported by Matterhorn core

Change-Id: Iec652f1c6d6b6a9bf118ba682276a7c70a6abc0d
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>

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lib: el3_runtime: Fix SPE system registers in el2_sysregs_context

Include EL2 registers related to SPE in EL2 context save/restore
routines if architecture supports it and platform wants to use thes

lib: el3_runtime: Fix SPE system registers in el2_sysregs_context

Include EL2 registers related to SPE in EL2 context save/restore
routines if architecture supports it and platform wants to use these
features in Secure world.

Change-Id: Ie01a2c38fa5f6c907276eddec120fdfb222561a6
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>

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lib: el3_runtime: Conditionally save/restore EL2 NEVE registers

Include EL2 registers related to Nested Virtualization in EL2 context
save/restore routines if architecture supports it and platform w

lib: el3_runtime: Conditionally save/restore EL2 NEVE registers

Include EL2 registers related to Nested Virtualization in EL2 context
save/restore routines if architecture supports it and platform wants to
use these features in Secure world.

Change-Id: If006ab83bbc2576488686f5ffdff88b91adced5c
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>

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lib: el3_runtime: Fix aarch32 system registers in el2_sysregs_context

AArch64-only platforms do not implement AArch32 at EL1 and higher ELs.
In such cases the build option CTX_INCLUDE_AARCH32_REGS i

lib: el3_runtime: Fix aarch32 system registers in el2_sysregs_context

AArch64-only platforms do not implement AArch32 at EL1 and higher ELs.
In such cases the build option CTX_INCLUDE_AARCH32_REGS is set to 0.
So don't save/restore aarch32 system registers in el2_sysregs_context
save/restore routines if CTX_INCLUDE_AARCH32_REGS is set to 0.

Change-Id: I229cdd46136c4b4bc9623b02eb444d904e09ce5a
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>

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plat: marvell: armada: Fix including plat/marvell/marvell.mk file

Include file plat/marvell/marvell.mk for platform A3700 was included two
times. Once from file plat/marvell/armada/a3k/common/a3700_

plat: marvell: armada: Fix including plat/marvell/marvell.mk file

Include file plat/marvell/marvell.mk for platform A3700 was included two
times. Once from file plat/marvell/armada/a3k/common/a3700_common.mk and
second time from common file plat/marvell/armada/common/marvell_common.mk.

It caused following warning every time was make called:

plat/marvell/marvell.mk:51: warning: overriding recipe for target 'mrvl_clean'
plat/marvell/marvell.mk:51: warning: ignoring old recipe for target 'mrvl_clean'

Change in this commit removes inclusion of plat/marvell/marvell.mk file in
common file plat/marvell/armada/common/marvell_common.mk. As a80x0 platform
needs this include file, add it also into a80x0 platform specific include
file lat/marvell/armada/a8k/common/a8k_common.mk.

Also moves inclusion of plat/marvell/marvell.mk file in a3700 platform file
plat/marvell/armada/a3k/common/a3700_common.mk at correct place. Global
plat/marvell/marvell.mk expects that variables DOIMAGEPATH and DOIMAGETOOL
are already defined, but it defines MARVELL_SECURE_BOOT variable which is
needed by plat/marvell/armada/a3k/common/a3700_common.mk.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I5cbbd7eb8a3376924419f9850516b2a4924be5aa

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Merge "fdts: add missing hash node in STM32MP157C-ED1 board DT" into integration

Merge "Increase type widths to satisfy width requirements" into integration

Merge changes Iba51bff1,I3f563cff into integration

* changes:
plat:qti Mandate SMC implementaion and bug fix
Update in coreboot_get_memory_type API to include size as well

Merge "docs: Remove deprecated information" into integration

Merge "docs: Update Release information for v2.5" into integration

Merge "docs: Update code freeze and release target date for v2.4" into integration

docs: Remove deprecated information

There are no references to AARCH32, AARCH64 and
__ASSEMBLY__ macros in the TF-A code hence
removed the deprecated information mentioning about
these macros in the

docs: Remove deprecated information

There are no references to AARCH32, AARCH64 and
__ASSEMBLY__ macros in the TF-A code hence
removed the deprecated information mentioning about
these macros in the document.

Change-Id: I472ab985ca2e4173bae23ff7b4465a9b60bc82eb
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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docs: Update Release information for v2.5

Updated tentative code freeze and release target date
for v2.5 release.

Change-Id: Idcfd9a127e9210846370dfa0685badac5b1c25c7
Signed-off-by: Manish V Badark

docs: Update Release information for v2.5

Updated tentative code freeze and release target date
for v2.5 release.

Change-Id: Idcfd9a127e9210846370dfa0685badac5b1c25c7
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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