1 /* 2 * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <string.h> 8 9 #include <arch_helpers.h> 10 #include <bl1/bl1.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <common/desc_image_load.h> 14 #include <drivers/console.h> 15 #include <drivers/io/io_driver.h> 16 #include <drivers/io/io_storage.h> 17 #include <libfdt.h> 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_defs.h> 20 #include <platform_def.h> 21 #include <plat/common/platform.h> 22 23 #include "avs_driver.h" 24 #include "board.h" 25 #include "boot_init_dram.h" 26 #include "cpg_registers.h" 27 #include "emmc_def.h" 28 #include "emmc_hal.h" 29 #include "emmc_std.h" 30 #include "io_common.h" 31 #include "io_rcar.h" 32 #include "qos_init.h" 33 #include "rcar_def.h" 34 #include "rcar_private.h" 35 #include "rcar_version.h" 36 #include "rom_api.h" 37 38 #define MAX_DRAM_CHANNELS 4 39 40 #if RCAR_BL2_DCACHE == 1 41 /* 42 * Following symbols are only used during plat_arch_setup() only 43 * when RCAR_BL2_DCACHE is enabled. 44 */ 45 static const uint64_t BL2_RO_BASE = BL_CODE_BASE; 46 static const uint64_t BL2_RO_LIMIT = BL_CODE_END; 47 48 #if USE_COHERENT_MEM 49 static const uint64_t BL2_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE; 50 static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END; 51 #endif /* USE_COHERENT_MEM */ 52 53 #endif /* RCAR_BL2_DCACHE */ 54 55 extern void plat_rcar_gic_driver_init(void); 56 extern void plat_rcar_gic_init(void); 57 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info); 58 extern void bl2_system_cpg_init(void); 59 extern void bl2_secure_setting(void); 60 extern void bl2_cpg_init(void); 61 extern void rcar_io_emmc_setup(void); 62 extern void rcar_io_setup(void); 63 extern void rcar_swdt_release(void); 64 extern void rcar_swdt_init(void); 65 extern void rcar_rpc_init(void); 66 extern void rcar_dma_init(void); 67 extern void rzg_pfc_init(void); 68 69 static void bl2_init_generic_timer(void); 70 71 /* RZ/G2 product check */ 72 #if RCAR_LSI == RZ_G2M 73 #define TARGET_PRODUCT PRR_PRODUCT_M3 74 #define TARGET_NAME "RZ/G2M" 75 #elif RCAR_LSI == RCAR_AUTO 76 #define TARGET_NAME "RZ/G2M" 77 #endif /* RCAR_LSI == RZ_G2M */ 78 79 #define GPIO_INDT (GPIO_INDT1) 80 #define GPIO_BKUP_TRG_SHIFT (1U << 8U) 81 82 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100) 83 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE), 84 assert_bl31_params_do_not_fit_in_shared_memory); 85 86 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 87 88 /* FDT with DRAM configuration */ 89 uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)]; 90 static void *fdt = (void *)fdt_blob; 91 92 static void unsigned_num_print(uint64_t unum, unsigned int radix, char *string) 93 { 94 /* Just need enough space to store 64 bit decimal integer */ 95 char num_buf[20]; 96 int i = 0; 97 unsigned int rem; 98 99 do { 100 rem = unum % radix; 101 if (rem < 0xaU) { 102 num_buf[i] = '0' + rem; 103 } else { 104 num_buf[i] = 'a' + (rem - 0xaU); 105 } 106 i++; 107 unum /= radix; 108 } while (unum > 0U); 109 110 while (--i >= 0) { 111 *string++ = num_buf[i]; 112 } 113 *string = 0; 114 } 115 116 #if RCAR_LOSSY_ENABLE == 1 117 typedef struct bl2_lossy_info { 118 uint32_t magic; 119 uint32_t a0; 120 uint32_t b0; 121 } bl2_lossy_info_t; 122 123 static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr, 124 uint64_t end_addr, uint32_t format, 125 uint32_t enable, int fcnlnode) 126 { 127 const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr); 128 char nodename[40] = { 0 }; 129 int ret, node; 130 131 /* Ignore undefined addresses */ 132 if (start_addr == 0UL && end_addr == 0UL) { 133 return; 134 } 135 136 snprintf(nodename, sizeof(nodename), "lossy-decompression@"); 137 unsigned_num_print(start_addr, 16, nodename + strlen(nodename)); 138 139 node = ret = fdt_add_subnode(fdt, fcnlnode, nodename); 140 if (ret < 0) { 141 NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret); 142 panic(); 143 } 144 145 ret = fdt_setprop_string(fdt, node, "compatible", 146 "renesas,lossy-decompression"); 147 if (ret < 0) { 148 NOTICE("BL2: Cannot add FCNL compat string %s (ret=%i)\n", 149 "renesas,lossy-decompression", ret); 150 panic(); 151 } 152 153 ret = fdt_appendprop_string(fdt, node, "compatible", 154 "shared-dma-pool"); 155 if (ret < 0) { 156 NOTICE("BL2: Cannot append FCNL compat string %s (ret=%i)\n", 157 "shared-dma-pool", ret); 158 panic(); 159 } 160 161 ret = fdt_setprop_u64(fdt, node, "reg", start_addr); 162 if (ret < 0) { 163 NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret); 164 panic(); 165 } 166 167 ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize)); 168 if (ret < 0) { 169 NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret); 170 panic(); 171 } 172 173 ret = fdt_setprop(fdt, node, "no-map", NULL, 0); 174 if (ret < 0) { 175 NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret); 176 panic(); 177 } 178 179 ret = fdt_setprop_u32(fdt, node, "renesas,formats", format); 180 if (ret < 0) { 181 NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret); 182 panic(); 183 } 184 } 185 186 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr, 187 uint64_t end_addr, uint32_t format, 188 uint32_t enable, int fcnlnode) 189 { 190 bl2_lossy_info_t info; 191 uint32_t reg; 192 193 bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode); 194 195 reg = format | (start_addr >> 20); 196 mmio_write_32(AXI_DCMPAREACRA0 + 0x8U * no, reg); 197 mmio_write_32(AXI_DCMPAREACRB0 + 0x8U * no, end_addr >> 20); 198 mmio_write_32(AXI_DCMPAREACRA0 + 0x8U * no, reg | enable); 199 200 info.magic = 0x12345678U; 201 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8U * no); 202 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8U * no); 203 204 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic); 205 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4U, info.a0); 206 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8U, info.b0); 207 208 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no, 209 mmio_read_32(AXI_DCMPAREACRA0 + 0x8U * no), 210 mmio_read_32(AXI_DCMPAREACRB0 + 0x8U * no)); 211 } 212 #endif /* RCAR_LOSSY_ENABLE == 1 */ 213 214 void bl2_plat_flush_bl31_params(void) 215 { 216 uint32_t product_cut, product, cut; 217 uint32_t boot_dev, boot_cpu; 218 uint32_t reg; 219 220 reg = mmio_read_32(RCAR_MODEMR); 221 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 222 223 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 224 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 225 emmc_terminate(); 226 } 227 228 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7) { 229 bl2_secure_setting(); 230 } 231 232 reg = mmio_read_32(RCAR_PRR); 233 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 234 product = reg & PRR_PRODUCT_MASK; 235 cut = reg & PRR_CUT_MASK; 236 237 if (!((product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) || 238 (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20))) { 239 /* Disable MFIS write protection */ 240 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1U); 241 } 242 243 reg = mmio_read_32(RCAR_MODEMR); 244 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 245 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 246 boot_cpu == MODEMR_BOOT_CPU_CA53) { 247 if (product_cut == PRR_PRODUCT_H3_CUT20) { 248 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 249 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE); 250 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 251 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE); 252 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE); 253 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE); 254 } else if (product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 255 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11)) { 256 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 257 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 258 } else if ((product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) || 259 (product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_11))) { 260 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 261 mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE); 262 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 263 } 264 265 if (product_cut == (PRR_PRODUCT_H3_CUT20) || 266 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 267 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11) || 268 product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) { 269 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE); 270 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE); 271 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE); 272 273 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE); 274 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE); 275 } 276 } 277 278 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE); 279 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT); 280 281 rcar_swdt_release(); 282 bl2_system_cpg_init(); 283 284 #if RCAR_BL2_DCACHE == 1 285 /* Disable data cache (clean and invalidate) */ 286 disable_mmu_el3(); 287 #endif /* RCAR_BL2_DCACHE == 1 */ 288 } 289 290 static uint32_t is_ddr_backup_mode(void) 291 { 292 #if RCAR_SYSTEM_SUSPEND 293 static uint32_t reason = RCAR_COLD_BOOT; 294 static uint32_t once; 295 296 if (once != 0U) { 297 return reason; 298 } 299 300 once = 1; 301 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0U) { 302 return reason; 303 } 304 305 reason = RCAR_WARM_BOOT; 306 return reason; 307 #else /* RCAR_SYSTEM_SUSPEND */ 308 return RCAR_COLD_BOOT; 309 #endif /* RCAR_SYSTEM_SUSPEND */ 310 } 311 312 int bl2_plat_handle_pre_image_load(unsigned int image_id) 313 { 314 u_register_t *boot_kind = (void *)BOOT_KIND_BASE; 315 bl_mem_params_node_t *bl_mem_params; 316 317 if (image_id != BL31_IMAGE_ID) { 318 return 0; 319 } 320 321 bl_mem_params = get_bl_mem_params_node(image_id); 322 323 if (is_ddr_backup_mode() != RCAR_COLD_BOOT) { 324 *boot_kind = RCAR_WARM_BOOT; 325 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 326 327 console_flush(); 328 bl2_plat_flush_bl31_params(); 329 330 /* will not return */ 331 bl2_enter_bl31(&bl_mem_params->ep_info); 332 } 333 334 *boot_kind = RCAR_COLD_BOOT; 335 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 336 337 return 0; 338 } 339 340 static uint64_t rzg_get_dest_addr_from_cert(uint32_t certid, uintptr_t *dest) 341 { 342 uint32_t cert, len; 343 int err; 344 345 err = rcar_get_certificate(certid, &cert); 346 if (err != 0) { 347 ERROR("%s : cert file load error", __func__); 348 return 1U; 349 } 350 351 rcar_read_certificate((uint64_t)cert, &len, dest); 352 353 return 0U; 354 } 355 356 int bl2_plat_handle_post_image_load(unsigned int image_id) 357 { 358 static bl2_to_bl31_params_mem_t *params; 359 bl_mem_params_node_t *bl_mem_params; 360 uintptr_t dest; 361 uint64_t ret; 362 363 if (params == NULL) { 364 params = (bl2_to_bl31_params_mem_t *)PARAMS_BASE; 365 memset((void *)PARAMS_BASE, 0, sizeof(*params)); 366 } 367 368 bl_mem_params = get_bl_mem_params_node(image_id); 369 370 switch (image_id) { 371 case BL31_IMAGE_ID: 372 ret = rzg_get_dest_addr_from_cert(SOC_FW_CONTENT_CERT_ID, 373 &dest); 374 if (ret == 0U) { 375 bl_mem_params->image_info.image_base = dest; 376 } 377 break; 378 case BL32_IMAGE_ID: 379 ret = rzg_get_dest_addr_from_cert(TRUSTED_OS_FW_CONTENT_CERT_ID, 380 &dest); 381 if (ret == 0U) { 382 bl_mem_params->image_info.image_base = dest; 383 } 384 385 memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info, 386 sizeof(entry_point_info_t)); 387 break; 388 case BL33_IMAGE_ID: 389 memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info, 390 sizeof(entry_point_info_t)); 391 break; 392 default: 393 break; 394 } 395 396 return 0; 397 } 398 399 struct meminfo *bl2_plat_sec_mem_layout(void) 400 { 401 return &bl2_tzram_layout; 402 } 403 404 static void bl2_populate_compatible_string(void *dt) 405 { 406 uint32_t board_type; 407 uint32_t board_rev; 408 uint32_t reg; 409 int ret; 410 411 fdt_setprop_u32(dt, 0, "#address-cells", 2); 412 fdt_setprop_u32(dt, 0, "#size-cells", 2); 413 414 /* Populate compatible string */ 415 rzg_get_board_type(&board_type, &board_rev); 416 switch (board_type) { 417 case BOARD_HIHOPE_RZ_G2M: 418 ret = fdt_setprop_string(dt, 0, "compatible", 419 "hoperun,hihope-rzg2m"); 420 break; 421 default: 422 NOTICE("BL2: Cannot set compatible string, board unsupported\n"); 423 panic(); 424 break; 425 } 426 427 if (ret < 0) { 428 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 429 panic(); 430 } 431 432 reg = mmio_read_32(RCAR_PRR); 433 switch (reg & PRR_PRODUCT_MASK) { 434 case PRR_PRODUCT_M3: 435 ret = fdt_appendprop_string(dt, 0, "compatible", 436 "renesas,r8a774a1"); 437 break; 438 default: 439 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n"); 440 panic(); 441 break; 442 } 443 444 if (ret < 0) { 445 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 446 panic(); 447 } 448 } 449 450 static void bl2_advertise_dram_entries(uint64_t dram_config[8]) 451 { 452 char nodename[32] = { 0 }; 453 uint64_t start, size; 454 uint64_t fdtsize; 455 int ret, node, chan; 456 457 for (chan = 0; chan < MAX_DRAM_CHANNELS; chan++) { 458 start = dram_config[2 * chan]; 459 size = dram_config[2 * chan + 1]; 460 if (size == 0U) { 461 continue; 462 } 463 464 NOTICE("BL2: CH%d: %llx - %llx, %lld %siB\n", 465 chan, start, start + size - 1U, 466 (size >> 30) ? : size >> 20, 467 (size >> 30) ? "G" : "M"); 468 } 469 470 /* 471 * We add the DT nodes in reverse order here. The fdt_add_subnode() 472 * adds the DT node before the first existing DT node, so we have 473 * to add them in reverse order to get nodes sorted by address in 474 * the resulting DT. 475 */ 476 for (chan = MAX_DRAM_CHANNELS - 1; chan >= 0; chan--) { 477 start = dram_config[2 * chan]; 478 size = dram_config[2 * chan + 1]; 479 if (size == 0U) { 480 continue; 481 } 482 483 /* 484 * Channel 0 is mapped in 32bit space and the first 485 * 128 MiB are reserved 486 */ 487 if (chan == 0) { 488 start = 0x48000000U; 489 size -= 0x8000000U; 490 } 491 492 fdtsize = cpu_to_fdt64(size); 493 494 snprintf(nodename, sizeof(nodename), "memory@"); 495 unsigned_num_print(start, 16, nodename + strlen(nodename)); 496 node = ret = fdt_add_subnode(fdt, 0, nodename); 497 if (ret < 0) { 498 goto err; 499 } 500 501 ret = fdt_setprop_string(fdt, node, "device_type", "memory"); 502 if (ret < 0) { 503 goto err; 504 } 505 506 ret = fdt_setprop_u64(fdt, node, "reg", start); 507 if (ret < 0) { 508 goto err; 509 } 510 511 ret = fdt_appendprop(fdt, node, "reg", &fdtsize, 512 sizeof(fdtsize)); 513 if (ret < 0) { 514 goto err; 515 } 516 } 517 518 return; 519 err: 520 NOTICE("BL2: Cannot add memory node to FDT (ret=%i)\n", ret); 521 panic(); 522 } 523 524 static void bl2_advertise_dram_size(uint32_t product) 525 { 526 uint64_t dram_config[8] = { 527 [0] = 0x400000000ULL, 528 [2] = 0x500000000ULL, 529 [4] = 0x600000000ULL, 530 [6] = 0x700000000ULL, 531 }; 532 533 switch (product) { 534 case PRR_PRODUCT_M3: 535 /* 4GB(2GBx2 2ch split) */ 536 dram_config[1] = 0x80000000ULL; 537 dram_config[5] = 0x80000000ULL; 538 break; 539 default: 540 NOTICE("BL2: Detected invalid DRAM entries\n"); 541 break; 542 } 543 544 bl2_advertise_dram_entries(dram_config); 545 } 546 547 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 548 u_register_t arg3, u_register_t arg4) 549 { 550 uint32_t reg, midr, boot_dev, boot_cpu, type, rev; 551 uint32_t product, product_cut, major, minor; 552 int32_t ret; 553 const char *str; 554 const char *unknown = "unknown"; 555 const char *cpu_ca57 = "CA57"; 556 const char *cpu_ca53 = "CA53"; 557 const char *product_g2m = "G2M"; 558 const char *boot_hyper80 = "HyperFlash(80MHz)"; 559 const char *boot_qspi40 = "QSPI Flash(40MHz)"; 560 const char *boot_qspi80 = "QSPI Flash(80MHz)"; 561 const char *boot_emmc25x1 = "eMMC(25MHz x1)"; 562 const char *boot_emmc50x8 = "eMMC(50MHz x8)"; 563 const char *boot_hyper160 = "HyperFlash(160MHz)"; 564 #if RZG_LCS_STATE_DETECTION_ENABLE 565 uint32_t lcs; 566 const char *lcs_secure = "SE"; 567 const char *lcs_cm = "CM"; 568 const char *lcs_dm = "DM"; 569 const char *lcs_sd = "SD"; 570 const char *lcs_fa = "FA"; 571 #endif /* RZG_LCS_STATE_DETECTION_ENABLE */ 572 573 #if (RCAR_LOSSY_ENABLE == 1) 574 int fcnlnode; 575 #endif /* (RCAR_LOSSY_ENABLE == 1) */ 576 577 bl2_init_generic_timer(); 578 579 reg = mmio_read_32(RCAR_MODEMR); 580 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 581 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 582 583 bl2_cpg_init(); 584 585 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 586 boot_cpu == MODEMR_BOOT_CPU_CA53) { 587 rzg_pfc_init(); 588 rcar_console_boot_init(); 589 } 590 591 plat_rcar_gic_driver_init(); 592 plat_rcar_gic_init(); 593 rcar_swdt_init(); 594 595 /* FIQ interrupts are taken to EL3 */ 596 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 597 598 write_daifclr(DAIF_FIQ_BIT); 599 600 reg = read_midr(); 601 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); 602 switch (midr) { 603 case MIDR_CA57: 604 str = cpu_ca57; 605 break; 606 case MIDR_CA53: 607 str = cpu_ca53; 608 break; 609 default: 610 str = unknown; 611 break; 612 } 613 614 NOTICE("BL2: RZ/G2 Initial Program Loader(%s) Rev.%s\n", str, 615 version_of_renesas); 616 617 reg = mmio_read_32(RCAR_PRR); 618 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 619 product = reg & PRR_PRODUCT_MASK; 620 621 switch (product) { 622 case PRR_PRODUCT_M3: 623 str = product_g2m; 624 break; 625 default: 626 str = unknown; 627 break; 628 } 629 630 if ((product == PRR_PRODUCT_M3) && 631 ((reg & RCAR_MAJOR_MASK) == PRR_PRODUCT_20)) { 632 if ((reg & PRR_CUT_MASK) == RCAR_M3_CUT_VER11) { 633 /* M3 Ver.1.1 or Ver.1.2 */ 634 NOTICE("BL2: PRR is RZ/%s Ver.1.1 / Ver.1.2\n", str); 635 } else { 636 NOTICE("BL2: PRR is RZ/%s Ver.1.%d\n", str, 637 (reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET); 638 } 639 } else { 640 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT; 641 major = major + RCAR_MAJOR_OFFSET; 642 minor = reg & RCAR_MINOR_MASK; 643 NOTICE("BL2: PRR is RZ/%s Ver.%d.%d\n", str, major, minor); 644 } 645 646 rzg_get_board_type(&type, &rev); 647 648 switch (type) { 649 case BOARD_HIHOPE_RZ_G2M: 650 break; 651 default: 652 type = BOARD_UNKNOWN; 653 break; 654 } 655 656 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN) { 657 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type)); 658 } else { 659 NOTICE("BL2: Board is %s Rev.%d.%d\n", 660 GET_BOARD_NAME(type), 661 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev)); 662 } 663 664 #if RCAR_LSI != RCAR_AUTO 665 if (product != TARGET_PRODUCT) { 666 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME); 667 ERROR("BL2: Please write the correct IPL to flash memory.\n"); 668 panic(); 669 } 670 #endif /* RCAR_LSI != RCAR_AUTO */ 671 rcar_avs_init(); 672 rcar_avs_setting(); 673 674 switch (boot_dev) { 675 case MODEMR_BOOT_DEV_HYPERFLASH160: 676 str = boot_hyper160; 677 break; 678 case MODEMR_BOOT_DEV_HYPERFLASH80: 679 str = boot_hyper80; 680 break; 681 case MODEMR_BOOT_DEV_QSPI_FLASH40: 682 str = boot_qspi40; 683 break; 684 case MODEMR_BOOT_DEV_QSPI_FLASH80: 685 str = boot_qspi80; 686 break; 687 case MODEMR_BOOT_DEV_EMMC_25X1: 688 str = boot_emmc25x1; 689 break; 690 case MODEMR_BOOT_DEV_EMMC_50X8: 691 str = boot_emmc50x8; 692 break; 693 default: 694 str = unknown; 695 break; 696 } 697 NOTICE("BL2: Boot device is %s\n", str); 698 699 rcar_avs_setting(); 700 701 #if RZG_LCS_STATE_DETECTION_ENABLE 702 reg = rcar_rom_get_lcs(&lcs); 703 if (reg != 0U) { 704 str = unknown; 705 goto lcm_state; 706 } 707 708 switch (lcs) { 709 case LCS_CM: 710 str = lcs_cm; 711 break; 712 case LCS_DM: 713 str = lcs_dm; 714 break; 715 case LCS_SD: 716 str = lcs_sd; 717 break; 718 case LCS_SE: 719 str = lcs_secure; 720 break; 721 case LCS_FA: 722 str = lcs_fa; 723 break; 724 default: 725 str = unknown; 726 break; 727 } 728 729 lcm_state: 730 NOTICE("BL2: LCM state is %s\n", str); 731 #endif /* RZG_LCS_STATE_DETECTION_ENABLE */ 732 733 rcar_avs_end(); 734 is_ddr_backup_mode(); 735 736 bl2_tzram_layout.total_base = BL31_BASE; 737 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE; 738 739 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 740 boot_cpu == MODEMR_BOOT_CPU_CA53) { 741 ret = rzg_dram_init(); 742 if (ret != 0) { 743 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret); 744 panic(); 745 } 746 rzg_qos_init(); 747 } 748 749 /* Set up FDT */ 750 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob)); 751 if (ret != 0) { 752 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret); 753 panic(); 754 } 755 756 /* Add platform compatible string */ 757 bl2_populate_compatible_string(fdt); 758 759 /* Print DRAM layout */ 760 bl2_advertise_dram_size(product); 761 762 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 763 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 764 if (rcar_emmc_init() != EMMC_SUCCESS) { 765 NOTICE("BL2: Failed to eMMC driver initialize.\n"); 766 panic(); 767 } 768 rcar_emmc_memcard_power(EMMC_POWER_ON); 769 if (rcar_emmc_mount() != EMMC_SUCCESS) { 770 NOTICE("BL2: Failed to eMMC mount operation.\n"); 771 panic(); 772 } 773 } else { 774 rcar_rpc_init(); 775 rcar_dma_init(); 776 } 777 778 reg = mmio_read_32(RST_WDTRSTCR); 779 reg &= ~WDTRSTCR_RWDT_RSTMSK; 780 reg |= WDTRSTCR_PASSWORD; 781 mmio_write_32(RST_WDTRSTCR, reg); 782 783 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); 784 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD); 785 786 reg = mmio_read_32(RCAR_PRR); 787 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57) { 788 mmio_write_32(CPG_CA57DBGRCR, 789 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR)); 790 } 791 792 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53) { 793 mmio_write_32(CPG_CA53DBGRCR, 794 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR)); 795 } 796 797 if (product_cut == PRR_PRODUCT_H3_CUT10) { 798 reg = mmio_read_32(CPG_PLL2CR); 799 reg &= ~((uint32_t)1 << 5); 800 mmio_write_32(CPG_PLL2CR, reg); 801 802 reg = mmio_read_32(CPG_PLL4CR); 803 reg &= ~((uint32_t)1 << 5); 804 mmio_write_32(CPG_PLL4CR, reg); 805 806 reg = mmio_read_32(CPG_PLL0CR); 807 reg &= ~((uint32_t)1 << 12); 808 mmio_write_32(CPG_PLL0CR, reg); 809 } 810 #if (RCAR_LOSSY_ENABLE == 1) 811 NOTICE("BL2: Lossy Decomp areas\n"); 812 813 fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory"); 814 if (fcnlnode < 0) { 815 NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n", 816 fcnlnode); 817 panic(); 818 } 819 820 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0, 821 LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode); 822 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1, 823 LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode); 824 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2, 825 LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode); 826 #endif /* RCAR_LOSSY_ENABLE */ 827 828 fdt_pack(fdt); 829 NOTICE("BL2: FDT at %p\n", fdt); 830 831 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 832 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 833 rcar_io_emmc_setup(); 834 } else { 835 rcar_io_setup(); 836 } 837 } 838 839 void bl2_el3_plat_arch_setup(void) 840 { 841 #if RCAR_BL2_DCACHE == 1 842 NOTICE("BL2: D-Cache enable\n"); 843 rcar_configure_mmu_el3(BL2_BASE, 844 BL2_END - BL2_BASE, 845 BL2_RO_BASE, BL2_RO_LIMIT 846 #if USE_COHERENT_MEM 847 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT 848 #endif /* USE_COHERENT_MEM */ 849 ); 850 #endif /* RCAR_BL2_DCACHE == 1 */ 851 } 852 853 void bl2_platform_setup(void) 854 { 855 /* 856 * Place holder for performing any platform initialization specific 857 * to BL2. 858 */ 859 } 860 861 static void bl2_init_generic_timer(void) 862 { 863 uint32_t reg_cntfid; 864 uint32_t modemr; 865 uint32_t modemr_pll; 866 uint32_t pll_table[] = { 867 EXTAL_MD14_MD13_TYPE_0, /* MD14/MD13 : 0b00 */ 868 EXTAL_MD14_MD13_TYPE_1, /* MD14/MD13 : 0b01 */ 869 EXTAL_MD14_MD13_TYPE_2, /* MD14/MD13 : 0b10 */ 870 EXTAL_MD14_MD13_TYPE_3 /* MD14/MD13 : 0b11 */ 871 }; 872 873 modemr = mmio_read_32(RCAR_MODEMR); 874 modemr_pll = (modemr & MODEMR_BOOT_PLL_MASK); 875 876 /* Set frequency data in CNTFID0 */ 877 reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT]; 878 879 /* Update memory mapped and register based frequency */ 880 write_cntfrq_el0((u_register_t)reg_cntfid); 881 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid); 882 /* Enable counter */ 883 mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF, 884 (uint32_t)CNTCR_EN); 885 } 886