Merge "fdts: use scmi_dvfs clock index 1 for cores 4-7" into integration

fdts: use scmi_dvfs clock index 1 for cores 4-7

This allows Matterhorn cores to operate at their optimal OPPs.

Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I2e1b784da10154a1f1f65dd0e3a

fdts: use scmi_dvfs clock index 1 for cores 4-7

This allows Matterhorn cores to operate at their optimal OPPs.

Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I2e1b784da10154a1f1f65dd0e3a39213e7683116

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plat/arm: Remove ARM_LINUX_KERNEL_AS_BL33 relying on RESET_TO_BL31

So far the ARM platform Makefile would require that RESET_TO_BL31 is set
when we ask for the ARM_LINUX_KERNEL_AS_BL33 feature.
Ther

plat/arm: Remove ARM_LINUX_KERNEL_AS_BL33 relying on RESET_TO_BL31

So far the ARM platform Makefile would require that RESET_TO_BL31 is set
when we ask for the ARM_LINUX_KERNEL_AS_BL33 feature.
There is no real technical reason for that, and the one place in the
code where this was needed has been fixed.

Remove the requirement of those two options to be always enabled
together.
This enables the direct kernel boot feature for the Foundation FVP
(as described in the documentation), which requires a BL1/FIP
combination to boot, so cannot use RESET_TO_BL31.

Change-Id: I6814797b6431b6614d684bab3c5830bfd9481851
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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plat/arm: Always allow ARM_LINUX_KERNEL_AS_BL33

At the moment we have the somewhat artifical limitation of
ARM_LINUX_KERNEL_AS_BL33 only being used together with RESET_TO_BL31.

However there does n

plat/arm: Always allow ARM_LINUX_KERNEL_AS_BL33

At the moment we have the somewhat artifical limitation of
ARM_LINUX_KERNEL_AS_BL33 only being used together with RESET_TO_BL31.

However there does not seem to be a good technical reason for that,
it was probably just to differentate between two different boot flows.

Move the initial register setup for ARM_LINUX_KERNEL_AS_BL33 out of the
RESET_TO_BL31 #ifdef, so that we initialise the registers in any case.

This allows to use a preloaded kernel image when using BL1 and FIP.

Change-Id: I832df272d3829f077661f4ee6d3dd9a276a0118f
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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tzc400: adjust filter flag if it is set to FILTER_BIT_ALL

TZC_400_REGION_ATTR_FILTER_BIT_ALL is a simple constant definition, so
it can't get the real filter number to construct the bit flag for all

tzc400: adjust filter flag if it is set to FILTER_BIT_ALL

TZC_400_REGION_ATTR_FILTER_BIT_ALL is a simple constant definition, so
it can't get the real filter number to construct the bit flag for all
existing filters. If the platform doesn't have 4 filters, passing
FILTER_BIT_ALL to tzc400_configure_region() will cause assertion or
misconfiguration. So adjust the bit flag against the real filter
number.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: Ie5c48303485f3b5015772961ee7c34746121ee84

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tzc400: fix logical error in FILTER_BIT definitions

The filters parameter passed to tzc400_configure_region() is supposed
to be filter bit flag without bit shift, so the macros
TZC_400_REGION_ATTR_F

tzc400: fix logical error in FILTER_BIT definitions

The filters parameter passed to tzc400_configure_region() is supposed
to be filter bit flag without bit shift, so the macros
TZC_400_REGION_ATTR_FILTER_BIT and TZC_400_REGION_ATTR_FILTER_BIT_ALL
should always construct the value without any shift.

It is not a functional issue for TZC_REGION_ATTR_F_EN_SHIFT is lucky
to be 0.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I5d363c462b8517256523f637e670eefa56722afd

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morello: Modify morello_plat_info structure

The structure has been modified to specify the memory
size in bytes instead of Gigabytes.

Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-off-by

morello: Modify morello_plat_info structure

The structure has been modified to specify the memory
size in bytes instead of Gigabytes.

Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Change-Id: I3384677d79af4f3cf55d3c353b6c20bb827b5ae7

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Merge "ddr: stm32mp1_ddr: correct SELFREF_TO_X32 mask" into integration

Merge "rainier: remove cpu workaround for errata 1542419" into integration

Merge "Add TRNG Firmware Interface service" into integration

Add TRNG Firmware Interface service

This adds the TRNG Firmware Interface Service to the standard
service dispatcher. This includes a method for dispatching entropy
requests to platforms and include

Add TRNG Firmware Interface service

This adds the TRNG Firmware Interface Service to the standard
service dispatcher. This includes a method for dispatching entropy
requests to platforms and includes an entropy pool implementation to
avoid dropping any entropy requested from the platform.

Change-Id: I71cadb3cb377a507652eca9e0d68714c973026e9
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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rainier: remove cpu workaround for errata 1542419

This patch removes the Neoverse N1 CPU errata workaround for
bug 1542419 as the bug is not present in Rainier R0P0 core.

Change-Id: Icaca299b13ef83

rainier: remove cpu workaround for errata 1542419

This patch removes the Neoverse N1 CPU errata workaround for
bug 1542419 as the bug is not present in Rainier R0P0 core.

Change-Id: Icaca299b13ef830b2ee5129576aae655a6288e69
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>

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ddr: stm32mp1_ddr: correct SELFREF_TO_X32 mask

In DDR controller PWRTMG register, the mask for field SELFREF_TO_X32 is
wrong. This field is from bit 16 to 23.

Change-Id: Id336fb08c88f0a153df186dd81

ddr: stm32mp1_ddr: correct SELFREF_TO_X32 mask

In DDR controller PWRTMG register, the mask for field SELFREF_TO_X32 is
wrong. This field is from bit 16 to 23.

Change-Id: Id336fb08c88f0a153df186dd819e41af72febb88
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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plat/qemu: trigger reboot with secure pl061

Secure pl061 qemu driver allows to rize the GPIO pin
from the secure world to reboot and power down
virtual machine.

Do not define secure-gpio for sbsa-r

plat/qemu: trigger reboot with secure pl061

Secure pl061 qemu driver allows to rize the GPIO pin
from the secure world to reboot and power down
virtual machine.

Do not define secure-gpio for sbsa-ref platform due to
reboot is done via sbsa-ec watchdog.

Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
Change-Id: I508d7c5cf4c75cb169b34b00682a76f6761d3869

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qti: spmi_arb: Fix NUM_APID and REG_APID_MAP() argument

The NUM_APID value was derived from kernel device tree sources, but I
made a conversion mistake: the amount of bytes in the APID map is the
to

qti: spmi_arb: Fix NUM_APID and REG_APID_MAP() argument

The NUM_APID value was derived from kernel device tree sources, but I
made a conversion mistake: the amount of bytes in the APID map is the
total size of the "core" register range (0x1100) minus the offset of the
APID map in that range (0x900). This is of course 0x1100 - 0x900 = 0x800
and not 0x200, so the amount of 4-byte integers it can fit is not 0x80
but 0x200. Fix this and make the math more explicit so it can be more
easily factored out and adjusted if that becomes necessary for a future
SoC.

Also fix a dangerous typo in REG_APID_MAP() where the macro would
reference a random variable `i` rather than its argument (`apid`), and
we just got lucky that the only caller in the current code happened to
pass in a variable called `i` as that argument.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I049dd044fa5aeb65be0e7b12150afd6eb4bac0fa

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libc: Import strtoull from FreeBSD project

From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
The coding guidelines[1] in TF-A forbid the use of ato*() functions
in favour of strto*(). However, t

libc: Import strtoull from FreeBSD project

From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
The coding guidelines[1] in TF-A forbid the use of ato*() functions
in favour of strto*(). However, the TF-A libc does not provide an
implementation of strto*(), making this rule impossible to satisfy.

Also made small changes to fit into TF-A project. Added the source
files to the libc makefile

[1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution

Change-Id: I2e94a0b227ec39f6f4530dc50bb477999d27730f
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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libc: Import strtoll from FreeBSD project

From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
The coding guidelines[1] in TF-A forbid the use of ato*() functions
in favour of strto*(). However, th

libc: Import strtoll from FreeBSD project

From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
The coding guidelines[1] in TF-A forbid the use of ato*() functions
in favour of strto*(). However, the TF-A libc does not provide an
implementation of strto*(), making this rule impossible to satisfy.

Also made small changes to fit into TF-A project. Added the source
files to the libc makefile

[1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution

Change-Id: I9cb581574d46de73c3d6917ebf78935fc5ac075a
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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libc: Import strtoul from FreeBSD project

From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
The coding guidelines[1] in TF-A forbid the use of ato*() functions
in favour of strto*(). However, th

libc: Import strtoul from FreeBSD project

From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
The coding guidelines[1] in TF-A forbid the use of ato*() functions
in favour of strto*(). However, the TF-A libc does not provide an
implementation of strto*(), making this rule impossible to satisfy.

Also made small changes to fit into TF-A project. Added the source
files to the libc makefile

[1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution

Change-Id: I8c3b92751d1ce226c966f7c81fedd83f0846865e
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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libc: Import strtol from FreeBSD project

From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
The coding guidelines[1] in TF-A forbid the use of ato*() functions
in favour of strto*(). However, the

libc: Import strtol from FreeBSD project

From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
The coding guidelines[1] in TF-A forbid the use of ato*() functions
in favour of strto*(). However, the TF-A libc does not provide an
implementation of strto*(), making this rule impossible to satisfy.

Also made small changes to fit into TF-A project. Added the source
files to the libc makefile

[1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution

Change-Id: Ica95bf5da722913834fe90bf3fe743aa34e01e80
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge changes from topic "RD_INFRA_POWER_MODING" into integration

* changes:
plat/arm/board: enable AMU for RD-N2
plat/arm/board: enable AMU for RD-V1
plat/arm/sgi: allow all PSCI callbacks on

Merge changes from topic "RD_INFRA_POWER_MODING" into integration

* changes:
plat/arm/board: enable AMU for RD-N2
plat/arm/board: enable AMU for RD-V1
plat/arm/sgi: allow all PSCI callbacks on RD-V1

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Merge "plat/arm:juno: fix parallel build issue for romlib config" into integration

Merge "product/tc0: Enable Theodul DSU in TC platform" into integration

drivers/gicv3: also shift eSPI register offset in GICD_OFFSET_64()

ESPI register offset should also be shifted right by REG##R_SHIFT to
keep consistent.

It is not a functional issue, for GICD_OFFSE

drivers/gicv3: also shift eSPI register offset in GICD_OFFSET_64()

ESPI register offset should also be shifted right by REG##R_SHIFT to
keep consistent.

It is not a functional issue, for GICD_OFFSET_64() is only used for
GICD_IROUTER<E>, and IROUTER_SHIFT is 0.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I76eee5c50e4300890e78e80bddde135ce88daa2d

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drivers/gicv3: add debug log for maximum INTID of SPI and eSPI

Add debug log for the maximum supported INTID of SPI and eSPI on the
current GIC implementation.

Signed-off-by: Heyi Guo <guoheyi@linu

drivers/gicv3: add debug log for maximum INTID of SPI and eSPI

Add debug log for the maximum supported INTID of SPI and eSPI on the
current GIC implementation.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: Ie45ab1d85b39658c4ca4bc54ee433ac44e41d03f

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drivers/gicv3: limit SPI ID to avoid misjudgement in GICD_OFFSET()

The GICv3 architecture allows GICD_TYPER.ITLinesNumber to be 31, so
the maximum possible value for num_ints is 1024. The value must

drivers/gicv3: limit SPI ID to avoid misjudgement in GICD_OFFSET()

The GICv3 architecture allows GICD_TYPER.ITLinesNumber to be 31, so
the maximum possible value for num_ints is 1024. The value must be
limited to (MAX_SPI_ID + 1), or GICD_OFFSET() will consider it as ESPI
INTID and return wrong register address.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: Iddcb83d3e5d241b39f4176c19c2bceaa2c3dd653

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