1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <common/interrupt_props.h> 13 #include <drivers/arm/gic_common.h> 14 15 #include "../common/gic_common_private.h" 16 #include "gicv3_private.h" 17 18 /****************************************************************************** 19 * This function marks the core as awake in the re-distributor and 20 * ensures that the interface is active. 21 *****************************************************************************/ 22 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base) 23 { 24 /* 25 * The WAKER_PS_BIT should be changed to 0 26 * only when WAKER_CA_BIT is 1. 27 */ 28 assert((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U); 29 30 /* Mark the connected core as awake */ 31 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_PS_BIT); 32 33 /* Wait till the WAKER_CA_BIT changes to 0 */ 34 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U) { 35 } 36 } 37 38 /****************************************************************************** 39 * This function marks the core as asleep in the re-distributor and ensures 40 * that the interface is quiescent. 41 *****************************************************************************/ 42 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base) 43 { 44 /* Mark the connected core as asleep */ 45 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_PS_BIT); 46 47 /* Wait till the WAKER_CA_BIT changes to 1 */ 48 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) == 0U) { 49 } 50 } 51 52 /******************************************************************************* 53 * This function probes the Redistributor frames when the driver is initialised 54 * and saves their base addresses. These base addresses are used later to 55 * initialise each Redistributor interface. 56 ******************************************************************************/ 57 void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs, 58 unsigned int rdistif_num, 59 uintptr_t gicr_base, 60 mpidr_hash_fn mpidr_to_core_pos) 61 { 62 u_register_t mpidr; 63 unsigned int proc_num; 64 uint64_t typer_val; 65 uintptr_t rdistif_base = gicr_base; 66 67 assert(rdistif_base_addrs != NULL); 68 69 /* 70 * Iterate over the Redistributor frames. Store the base address of each 71 * frame in the platform provided array. Use the "Processor Number" 72 * field to index into the array if the platform has not provided a hash 73 * function to convert an MPIDR (obtained from the "Affinity Value" 74 * field into a linear index. 75 */ 76 do { 77 typer_val = gicr_read_typer(rdistif_base); 78 if (mpidr_to_core_pos != NULL) { 79 mpidr = mpidr_from_gicr_typer(typer_val); 80 proc_num = mpidr_to_core_pos(mpidr); 81 } else { 82 proc_num = (typer_val >> TYPER_PROC_NUM_SHIFT) & 83 TYPER_PROC_NUM_MASK; 84 } 85 86 if (proc_num < rdistif_num) { 87 rdistif_base_addrs[proc_num] = rdistif_base; 88 } 89 90 rdistif_base += (1U << GICR_PCPUBASE_SHIFT); 91 } while ((typer_val & TYPER_LAST_BIT) == 0U); 92 } 93 94 /******************************************************************************* 95 * Helper function to configure the default attributes of (E)SPIs. 96 ******************************************************************************/ 97 void gicv3_spis_config_defaults(uintptr_t gicd_base) 98 { 99 unsigned int i, num_ints; 100 #if GIC_EXT_INTID 101 unsigned int num_eints; 102 #endif 103 unsigned int typer_reg = gicd_read_typer(gicd_base); 104 105 /* Maximum SPI INTID is 32 * (GICD_TYPER.ITLinesNumber + 1) - 1 */ 106 num_ints = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5; 107 108 /* 109 * The GICv3 architecture allows GICD_TYPER.ITLinesNumber to be 31, so 110 * the maximum possible value for num_ints is 1024. Limit the value to 111 * MAX_SPI_ID + 1 to avoid getting wrong address in GICD_OFFSET() macro. 112 */ 113 if (num_ints > MAX_SPI_ID + 1U) { 114 num_ints = MAX_SPI_ID + 1U; 115 } 116 117 /* Treat all (E)SPIs as G1NS by default. We do 32 at a time. */ 118 for (i = MIN_SPI_ID; i < num_ints; i += (1U << IGROUPR_SHIFT)) { 119 gicd_write_igroupr(gicd_base, i, ~0U); 120 } 121 122 #if GIC_EXT_INTID 123 /* Check if extended SPI range is implemented */ 124 if ((typer_reg & TYPER_ESPI) != 0U) { 125 /* 126 * Maximum ESPI INTID is 32 * (GICD_TYPER.ESPI_range + 1) + 4095 127 */ 128 num_eints = ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) & 129 TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID; 130 131 for (i = MIN_ESPI_ID; i < num_eints; 132 i += (1U << IGROUPR_SHIFT)) { 133 gicd_write_igroupr(gicd_base, i, ~0U); 134 } 135 } else { 136 num_eints = 0U; 137 } 138 #endif 139 140 /* Setup the default (E)SPI priorities doing four at a time */ 141 for (i = MIN_SPI_ID; i < num_ints; i += (1U << IPRIORITYR_SHIFT)) { 142 gicd_write_ipriorityr(gicd_base, i, GICD_IPRIORITYR_DEF_VAL); 143 } 144 145 #if GIC_EXT_INTID 146 for (i = MIN_ESPI_ID; i < num_eints; 147 i += (1U << IPRIORITYR_SHIFT)) { 148 gicd_write_ipriorityr(gicd_base, i, GICD_IPRIORITYR_DEF_VAL); 149 } 150 #endif 151 /* 152 * Treat all (E)SPIs as level triggered by default, write 16 at a time 153 */ 154 for (i = MIN_SPI_ID; i < num_ints; i += (1U << ICFGR_SHIFT)) { 155 gicd_write_icfgr(gicd_base, i, 0U); 156 } 157 158 #if GIC_EXT_INTID 159 for (i = MIN_ESPI_ID; i < num_eints; i += (1U << ICFGR_SHIFT)) { 160 gicd_write_icfgr(gicd_base, i, 0U); 161 } 162 #endif 163 } 164 165 /******************************************************************************* 166 * Helper function to configure properties of secure (E)SPIs 167 ******************************************************************************/ 168 unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base, 169 const interrupt_prop_t *interrupt_props, 170 unsigned int interrupt_props_num) 171 { 172 unsigned int i; 173 const interrupt_prop_t *current_prop; 174 unsigned long long gic_affinity_val; 175 unsigned int ctlr_enable = 0U; 176 177 /* Make sure there's a valid property array */ 178 if (interrupt_props_num > 0U) { 179 assert(interrupt_props != NULL); 180 } 181 182 for (i = 0U; i < interrupt_props_num; i++) { 183 current_prop = &interrupt_props[i]; 184 185 unsigned int intr_num = current_prop->intr_num; 186 187 /* Skip SGI, (E)PPI and LPI interrupts */ 188 if (!IS_SPI(intr_num)) { 189 continue; 190 } 191 192 /* Configure this interrupt as a secure interrupt */ 193 gicd_clr_igroupr(gicd_base, intr_num); 194 195 /* Configure this interrupt as G0 or a G1S interrupt */ 196 assert((current_prop->intr_grp == INTR_GROUP0) || 197 (current_prop->intr_grp == INTR_GROUP1S)); 198 199 if (current_prop->intr_grp == INTR_GROUP1S) { 200 gicd_set_igrpmodr(gicd_base, intr_num); 201 ctlr_enable |= CTLR_ENABLE_G1S_BIT; 202 } else { 203 gicd_clr_igrpmodr(gicd_base, intr_num); 204 ctlr_enable |= CTLR_ENABLE_G0_BIT; 205 } 206 207 /* Set interrupt configuration */ 208 gicd_set_icfgr(gicd_base, intr_num, current_prop->intr_cfg); 209 210 /* Set the priority of this interrupt */ 211 gicd_set_ipriorityr(gicd_base, intr_num, 212 current_prop->intr_pri); 213 214 /* Target (E)SPIs to the primary CPU */ 215 gic_affinity_val = 216 gicd_irouter_val_from_mpidr(read_mpidr(), 0U); 217 gicd_write_irouter(gicd_base, intr_num, 218 gic_affinity_val); 219 220 /* Enable this interrupt */ 221 gicd_set_isenabler(gicd_base, intr_num); 222 } 223 224 return ctlr_enable; 225 } 226 227 /******************************************************************************* 228 * Helper function to configure the default attributes of (E)SPIs 229 ******************************************************************************/ 230 void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base) 231 { 232 unsigned int i, ppi_regs_num, regs_num; 233 234 #if GIC_EXT_INTID 235 /* Calculate number of PPI registers */ 236 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >> 237 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1; 238 /* All other values except PPInum [0-2] are reserved */ 239 if (ppi_regs_num > 3U) { 240 ppi_regs_num = 1U; 241 } 242 #else 243 ppi_regs_num = 1U; 244 #endif 245 /* 246 * Disable all SGIs (imp. def.)/(E)PPIs before configuring them. 247 * This is a more scalable approach as it avoids clearing 248 * the enable bits in the GICD_CTLR. 249 */ 250 for (i = 0U; i < ppi_regs_num; ++i) { 251 gicr_write_icenabler(gicr_base, i, ~0U); 252 } 253 254 /* Wait for pending writes to GICR_ICENABLER */ 255 gicr_wait_for_pending_write(gicr_base); 256 257 /* 32 interrupt IDs per GICR_IGROUPR register */ 258 for (i = 0U; i < ppi_regs_num; ++i) { 259 /* Treat all SGIs/(E)PPIs as G1NS by default */ 260 gicr_write_igroupr(gicr_base, i, ~0U); 261 } 262 263 /* 4 interrupt IDs per GICR_IPRIORITYR register */ 264 regs_num = ppi_regs_num << 3; 265 for (i = 0U; i < regs_num; ++i) { 266 /* Setup the default (E)PPI/SGI priorities doing 4 at a time */ 267 gicr_write_ipriorityr(gicr_base, i, GICD_IPRIORITYR_DEF_VAL); 268 } 269 270 /* 16 interrupt IDs per GICR_ICFGR register */ 271 regs_num = ppi_regs_num << 1; 272 for (i = (MIN_PPI_ID >> ICFGR_SHIFT); i < regs_num; ++i) { 273 /* Configure all (E)PPIs as level triggered by default */ 274 gicr_write_icfgr(gicr_base, i, 0U); 275 } 276 } 277 278 /******************************************************************************* 279 * Helper function to configure properties of secure G0 and G1S (E)PPIs and SGIs 280 ******************************************************************************/ 281 unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base, 282 const interrupt_prop_t *interrupt_props, 283 unsigned int interrupt_props_num) 284 { 285 unsigned int i; 286 const interrupt_prop_t *current_prop; 287 unsigned int ctlr_enable = 0U; 288 289 /* Make sure there's a valid property array */ 290 if (interrupt_props_num > 0U) { 291 assert(interrupt_props != NULL); 292 } 293 294 for (i = 0U; i < interrupt_props_num; i++) { 295 current_prop = &interrupt_props[i]; 296 297 unsigned int intr_num = current_prop->intr_num; 298 299 /* Skip (E)SPI interrupt */ 300 if (!IS_SGI_PPI(intr_num)) { 301 continue; 302 } 303 304 /* Configure this interrupt as a secure interrupt */ 305 gicr_clr_igroupr(gicr_base, intr_num); 306 307 /* Configure this interrupt as G0 or a G1S interrupt */ 308 assert((current_prop->intr_grp == INTR_GROUP0) || 309 (current_prop->intr_grp == INTR_GROUP1S)); 310 311 if (current_prop->intr_grp == INTR_GROUP1S) { 312 gicr_set_igrpmodr(gicr_base, intr_num); 313 ctlr_enable |= CTLR_ENABLE_G1S_BIT; 314 } else { 315 gicr_clr_igrpmodr(gicr_base, intr_num); 316 ctlr_enable |= CTLR_ENABLE_G0_BIT; 317 } 318 319 /* Set the priority of this interrupt */ 320 gicr_set_ipriorityr(gicr_base, intr_num, 321 current_prop->intr_pri); 322 323 /* 324 * Set interrupt configuration for (E)PPIs. 325 * Configurations for SGIs 0-15 are ignored. 326 */ 327 if (intr_num >= MIN_PPI_ID) { 328 gicr_set_icfgr(gicr_base, intr_num, 329 current_prop->intr_cfg); 330 } 331 332 /* Enable this interrupt */ 333 gicr_set_isenabler(gicr_base, intr_num); 334 } 335 336 return ctlr_enable; 337 } 338 339 /** 340 * gicv3_rdistif_get_number_frames() - determine size of GICv3 GICR region 341 * @gicr_frame: base address of the GICR region to check 342 * 343 * This iterates over the GICR_TYPER registers of multiple GICR frames in 344 * a GICR region, to find the instance which has the LAST bit set. For most 345 * systems this corresponds to the number of cores handled by a redistributor, 346 * but there could be disabled cores among them. 347 * It assumes that each GICR region is fully accessible (till the LAST bit 348 * marks the end of the region). 349 * If a platform has multiple GICR regions, this function would need to be 350 * called multiple times, providing the respective GICR base address each time. 351 * 352 * Return: number of valid GICR frames (at least 1, up to PLATFORM_CORE_COUNT) 353 ******************************************************************************/ 354 unsigned int gicv3_rdistif_get_number_frames(const uintptr_t gicr_frame) 355 { 356 uintptr_t rdistif_base = gicr_frame; 357 unsigned int count; 358 359 for (count = 1; count < PLATFORM_CORE_COUNT; count++) { 360 if ((gicr_read_typer(rdistif_base) & TYPER_LAST_BIT) != 0U) { 361 break; 362 } 363 rdistif_base += (1U << GICR_PCPUBASE_SHIFT); 364 } 365 366 return count; 367 } 368