Fix static analysis defects

Fixed a Coverity defect by adding a runtime check to avoid potential
NULL pointer dereference.

Change-Id: I9a0aa0efd27334131ac835b43348658b436c657d
Signed-off-by: John T

Fix static analysis defects

Fixed a Coverity defect by adding a runtime check to avoid potential
NULL pointer dereference.

Change-Id: I9a0aa0efd27334131ac835b43348658b436c657d
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

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hikey960: fix build issue for clang

plat/hisilicon/hikey960/include/plat_macros.S:19:55: error: unexpected token in
'.asciz' directive
.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" " Offset:

hikey960: fix build issue for clang

plat/hisilicon/hikey960/include/plat_macros.S:19:55: error: unexpected token in
'.asciz' directive
.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" " Offset:\t\t\tvalue\n"
^
Makefile:720: recipe for target 'build/hikey960/debug/bl1/cortex_a53.o' failed
make: *** [build/hikey960/debug/bl1/cortex_a53.o] Error 1

Merge the two lines into one.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

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hikey: fix build issue for clang

plat/hisilicon/hikey/include/plat_macros.S:19:55: error: unexpected token in '.asciz' directive
.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" " Offset:\t\t\t

hikey: fix build issue for clang

plat/hisilicon/hikey/include/plat_macros.S:19:55: error: unexpected token in '.asciz' directive
.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" " Offset:\t\t\tvalue\n"
^
Makefile:720: recipe for target 'build/hikey/debug/bl1/cortex_a53.o' failed
make: *** [build/hikey/debug/bl1/cortex_a53.o] Error 1

Merge two lines into one line.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

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sgm: increase SCP_BL2 maximum size

For sgm775 the SCP_BL2 build in debug mode is around 94KiB which
is higher than the maximum size for SCP_BL2.

This patch increase the maximum allowed size for SCP

sgm: increase SCP_BL2 maximum size

For sgm775 the SCP_BL2 build in debug mode is around 94KiB which
is higher than the maximum size for SCP_BL2.

This patch increase the maximum allowed size for SCP_BL2 to
96KiB.

Change-Id: Ibca0daadba41429301c651ae21cbba87e45ccddf
Signed-off-by: Elieva Pignat <Elieva.Pignat@arm.com>

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Ensure the flow through switch statements is clear

Ensure case clauses:
* Terminate with an unconditional break, return or goto statement.
* Use conditional break, return or goto statements as l

Ensure the flow through switch statements is clear

Ensure case clauses:
* Terminate with an unconditional break, return or goto statement.
* Use conditional break, return or goto statements as long as the end
of the case clause is unreachable; such case clauses must terminate
with assert(0) /* Unreachable */ or an unconditional __dead2 function
call
* Only fallthough when doing otherwise would result in less
readable/maintainable code; such case clauses must terminate with a
/* Fallthrough */ comment to make it clear this is the case and
indicate that a fallthrough is intended.

This reduces the chance of bugs appearing due to unintended flow through a
switch statement

Change-Id: I70fc2d1f4fd679042397dec12fd1982976646168
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

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plat/arm: Enable MULTI_CONSOLE_API in AArch32

Set MULTI_CONSOLE_API=1 for both AArch64 and AArch32 by default.
MULTI_CONSOLE_API=0 is still supported, but it has to be set from the
command line.

Ch

plat/arm: Enable MULTI_CONSOLE_API in AArch32

Set MULTI_CONSOLE_API=1 for both AArch64 and AArch32 by default.
MULTI_CONSOLE_API=0 is still supported, but it has to be set from the
command line.

Change-Id: I4eeaa8e243a3fe93ed8a716e502666a26ad28f35
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

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pl011: Add support in AArch32 for MULTI_CONSOLE_API

Allow AArch32 to use the multi console driver by adding the
required functions

Change-Id: I9e69f18965f320074cf75442d6b0de891aef7936
Signed-off-by

pl011: Add support in AArch32 for MULTI_CONSOLE_API

Allow AArch32 to use the multi console driver by adding the
required functions

Change-Id: I9e69f18965f320074cf75442d6b0de891aef7936
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

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Merge pull request #1570 from Andre-ARM/allwinner/pmic-fixes

Allwinner PMIC fixes

drivers: i2c: mentor: move platform code into header files

At the moment we have two I2C stub drivers (for the Allwinner and the
Marvell platform), which #include the actual .c driver file.
Change t

drivers: i2c: mentor: move platform code into header files

At the moment we have two I2C stub drivers (for the Allwinner and the
Marvell platform), which #include the actual .c driver file.
Change this into the more usual design, by renaming and moving the stub
drivers into platform specific header files and including these from the
actual driver file. The platform specific include directories make sure
the driver picks up the right header automatically.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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ARM platforms: Reintroduce coherent memory for BL1 and BL2

The patch d323af9 removed the support for coherent memory in BL1 and
BL2 for ARM platforms. But the CryptoCell SBROM integration depends
o

ARM platforms: Reintroduce coherent memory for BL1 and BL2

The patch d323af9 removed the support for coherent memory in BL1 and
BL2 for ARM platforms. But the CryptoCell SBROM integration depends
on use of coherent buffers for passing data from the AP CPU to the
CryptoCell. Hence this patch reintroduces support for coherent
memory in BL1 and BL2 if ARM_CRYPTOCELL_INTEG=1.

Change-Id: I011482dda7f7a3ec9e3e79bfb3f4fa03796f7e02
Signed-Off-by: Soby Mathew <soby.mathew@arm.com>

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allwinner: sun50i_h6: initialise I2C just before powering down

Even though we initialise the platform part and the I2C controller
itself at boot time, we actually only access the bus on power down.

allwinner: sun50i_h6: initialise I2C just before powering down

Even though we initialise the platform part and the I2C controller
itself at boot time, we actually only access the bus on power down.
Meanwhile a rich OS might have configured the I2C pins differently or
even disabled the controller.
So repeat the platform setup and controller initialisation just before
we actually access the bus to power off the system. This is safe,
because at this point the rich OS should no longer be running.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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allwinner: sun50i_h6: improve I2C setup

Drop the unnecessary check for the I2C pins being already configured as
I2C pins (we actually don't care).
Also avoid resetting *every* peripheral that is cov

allwinner: sun50i_h6: improve I2C setup

Drop the unnecessary check for the I2C pins being already configured as
I2C pins (we actually don't care).
Also avoid resetting *every* peripheral that is covered by the PRCM reset
controller, instead just clear the one line connected to the I2C controller.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge pull request #1569 from soby-mathew/sm/cov_fix_scmi

CSS: Fix overrun if system power level is not available

CSS: Fix overrun if system power level is not available

This patch fixes an array overrun in CSS scmi driver if the
system power domain level is less than 2. This was reported from
https://scan.cove

CSS: Fix overrun if system power level is not available

This patch fixes an array overrun in CSS scmi driver if the
system power domain level is less than 2. This was reported from
https://scan.coverity.com/projects/arm-software-arm-trusted-firmware

CID 308492

Change-Id: I3a59c700490816718d20c71141281f19b2b7e7f7
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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Merge pull request #1555 from theopolis/tbb-hikey960

hikey960: Add development TBB support

Merge pull request #1534 from Icenowy/sun50i_h6_pmic

Add support for Allwinner H6 + X-Powers AXP805 PMIC combination

hikey960: Add development TBB support

This patch adds experimental support for TBB to the HiKey960 board. To
build and test with TBB modify the uefi-tools project platforms.config

+ATF_BUILDFLAGS=T

hikey960: Add development TBB support

This patch adds experimental support for TBB to the HiKey960 board. To
build and test with TBB modify the uefi-tools project platforms.config

+ATF_BUILDFLAGS=TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 SAVE_KEYS=1 \
MBEDTLS_DIR=./mbedtls

Signed-off-by: Teddy Reed <teddy@casualhacking.io>

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Merge pull request #1566 from EvanLloyd/non_secure_uart

ARM Platforms:Enable non-secure access to UART1

allwinner: implement system power down on H6 w/ AXP805

The AXP805 PMIC used with H6 is capable of shutting down the system.

Add support for using it to shut down the system power.

The original pla

allwinner: implement system power down on H6 w/ AXP805

The AXP805 PMIC used with H6 is capable of shutting down the system.

Add support for using it to shut down the system power.

The original placeholder power off code is moved to A64 code, as it's
still TODO to implement PMIC operations for A64.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

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allwinner: sun50i_h6: add initial AXP805 PMIC code

The OTT reference design of Allwinner H6 SoC uses an X-Powers AXP805
PMIC.

Add initial code for it.

Currently it's only detected.

Signed-off-by:

allwinner: sun50i_h6: add initial AXP805 PMIC code

The OTT reference design of Allwinner H6 SoC uses an X-Powers AXP805
PMIC.

Add initial code for it.

Currently it's only detected.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

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Merge pull request #1565 from satheesbalya-arm/sb1_2332_fwu_sds_register

juno: Revert FWU update detect mechanism

allwinner: call PMIC setup code

As the ATF may need to do some power initialization on Allwinner
platform with AXP PMICs, call the PMIC setup code in BL31.

Stub of PMIC setup code is added, to prev

allwinner: call PMIC setup code

As the ATF may need to do some power initialization on Allwinner
platform with AXP PMICs, call the PMIC setup code in BL31.

Stub of PMIC setup code is added, to prevent undefined reference.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

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juno: Revert FWU update detect mechanism

The patch 7b56928 unified the FWU mechanism on FVP and Juno
platforms due to issues with MCC firmware not preserving the
NVFLAGS. With MCCv150 firmware, this

juno: Revert FWU update detect mechanism

The patch 7b56928 unified the FWU mechanism on FVP and Juno
platforms due to issues with MCC firmware not preserving the
NVFLAGS. With MCCv150 firmware, this issue is resolved. Also
writing to the NOR flash while executing from the same flash
in Bypass mode had some stability issues. Hence, since the
MCC firmware issue is resolved, this patch reverts to the
NVFLAGS mechanism to detect FWU. Also, with the introduction
of SDS (Shared Data Structure) by the SCP, the reset syndrome
needs to queried from the appropriate SDS field.

Change-Id: If9c08f1afaaa4fcf197f3186887068103855f554
Signed-off-by: Sathees Balya <sathees.balya@arm.com>
Signed-off-by: Soby Mathew <Soby.Mathew@arm.com>

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ARM Platforms:Enable non-secure access to UART1

Adds an undocumented build option that enables non-secure access to
the PL011 UART1.
This allows a custom build where the UART can be used as a serial

ARM Platforms:Enable non-secure access to UART1

Adds an undocumented build option that enables non-secure access to
the PL011 UART1.
This allows a custom build where the UART can be used as a serial debug
port for WinDbg (or other debugger) connection.

This option is not documented in the user guide, as it is provided as a
convenience for Windows debugging, and not intended for general use.
In particular, enabling non-secure access to the UART might allow
a denial of service attack!

Change-Id: I4cd7d59c2cac897cc654ab5e1188ff031114ed3c
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>

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Add cache flush after BL1 writes heap info to DTB

A cache flush is added in BL1, in Mbed TLS shared heap code. Thus, we
ensure that the heap info written to the DTB always gets written back to
memor

Add cache flush after BL1 writes heap info to DTB

A cache flush is added in BL1, in Mbed TLS shared heap code. Thus, we
ensure that the heap info written to the DTB always gets written back to
memory. Hence, sharing this info with other images is guaranteed.

Change-Id: I0faada31fe7a83854cd5e2cf277ba519e3f050d5
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

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