plat/arm/sgi: add support for SGI-Clark platform

SGI-Clark platform is the next version in the Arm's SGI platform
series. One of the primary difference between the SGI-575 platform and
the SGI-Clark

plat/arm/sgi: add support for SGI-Clark platform

SGI-Clark platform is the next version in the Arm's SGI platform
series. One of the primary difference between the SGI-575 platform and
the SGI-Clark platform is the MHU version (MHUv2 in case of SGI-Clark).
Add the required base support for SGI-Clark platform.

Change-Id: If396e5279fdf801d586662dad0b55195e81371e4
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

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plat/arm/sgi: disable Ares cpu power down bit in reset handler

On SGI platforms that include Ares CPUs, the 'CORE_PWRDN_EN' bit of
'CPUPWRCTLR_EL1' register requires an explicit write to clear it to

plat/arm/sgi: disable Ares cpu power down bit in reset handler

On SGI platforms that include Ares CPUs, the 'CORE_PWRDN_EN' bit of
'CPUPWRCTLR_EL1' register requires an explicit write to clear it to
enable hotplug and idle to function correctly.

The reset value of the CORE_PWRDN_EN bit is zero but it still requires
this explicit clear to zero. This indicates that this could be a model
related issue but for now this issue can be fixed be clearing the
CORE_PWRDN_EN bit in the platform specific reset handler function.

Change-Id: I8b9884ae27a2986d789bfec2e9ae792ef930944e
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

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Merge pull request #1638 from chandnich/sgi575-update

Sgi575 update

Merge pull request #1636 from antonio-nino-diaz-arm/an/console

Deprecate weak crash console functions

Merge pull request #1640 from soby-mathew/sm/fin_con_reg

Multi-console: Deprecate the `finish_console_register` macro

Deprecate weak crash console functions

The default behaviour of the plat_crash_console_xxx functions isn't
obvious to someone that hasn't read all the documentation. As they are
not mandatory, it is

Deprecate weak crash console functions

The default behaviour of the plat_crash_console_xxx functions isn't
obvious to someone that hasn't read all the documentation. As they are
not mandatory, it is unlikely that the code will be checked when doing a
platform port, which may mean that some platforms may not have crash
console support at all.

The idea of this patch is to force platform maintainers to decide how
the crash console has to behave so that the final behaviour isn't
unexpected.

Change-Id: I40b2a7b56c5530c1dcd63eace5bd37ae6335056e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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rockchip: Use common crash console functions

This platform depends on weak functions defined in
``plat/common/aarch64/platform_helpers.S`` that are going to be removed.

Change-Id: I5104d091c32271d7

rockchip: Use common crash console functions

This platform depends on weak functions defined in
``plat/common/aarch64/platform_helpers.S`` that are going to be removed.

Change-Id: I5104d091c32271d77ed9690e9dc257c061289def
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Add sample crash console functions

Platforms that wish to use the sample functions have to add the file to
their Makefile. It is not included by default.

Change-Id: I713617bb58dc218967199248f68da86

Add sample crash console functions

Platforms that wish to use the sample functions have to add the file to
their Makefile. It is not included by default.

Change-Id: I713617bb58dc218967199248f68da86241d7ec40
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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plat/arm: Make crash console functions strong

In Arm platforms the crash console doesn't print anything if the crash
happens early enough. This happens in all images, not only BL1. The
reason is tha

plat/arm: Make crash console functions strong

In Arm platforms the crash console doesn't print anything if the crash
happens early enough. This happens in all images, not only BL1. The
reason is that they the files ``plat/common/aarch64/platform_helpers.S``
and ``plat/arm/common/aarch64/arm_helpers.S``, and the crash console
functions are defined as weak in both files. In practice, the linker
can pick the one in ``plat/common``, which simply switches the multi
console to crash mode when it wants to initialize the crash console.
In the case of Arm platforms, there are no console drivers registered
at that point, so nothing is printed.

This patch makes the functions in plat/arm strong so that they override
the weak functions in plat/common.

Change-Id: Id358db7d2567d7df0951790a695636cf6c9ac57f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Add plat_crash_console_flush to platforms without it

Even though at this point plat_crash_console_flush is optional, it will
stop being optional in a following patch.

The console driver of warp7 do

Add plat_crash_console_flush to platforms without it

Even though at this point plat_crash_console_flush is optional, it will
stop being optional in a following patch.

The console driver of warp7 doesn't support flush, so the implementation
is a placeholder.

TI had ``plat_crash_console_init`` and ``plat_crash_console_putc``, but
they weren't global so they weren't actually used. Also, they were
calling the wrong functions.

imx8_helpers.S only has placeholders for all of the functions.

Change-Id: I8d17bbf37c7dad74e134c61ceb92acb9af497718
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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zynqmp: Remove dependency on arm_helpers.S

Non-Arm platforms shouldn't use Arm platform code. This patch copies the
implementation of the functions in arm_helpers.S to zynqmp_helpers.S to
remove thi

zynqmp: Remove dependency on arm_helpers.S

Non-Arm platforms shouldn't use Arm platform code. This patch copies the
implementation of the functions in arm_helpers.S to zynqmp_helpers.S to
remove this dependency of zynqmp on Arm platforms.

Change-Id: Ia85f303c4c63bcf0ffa57c7f3ef9d88376729b6b
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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rpi3: Add mem reserve region to DTB if present

When a device tree blob is present at a known address, instead of, for
example, relying on the user modifying the Linux command line to warn
about the

rpi3: Add mem reserve region to DTB if present

When a device tree blob is present at a known address, instead of, for
example, relying on the user modifying the Linux command line to warn
about the memory reserved for the Trusted Firmware, pass it on the DTB.

The current code deletes the memory reserved for the default bootstrap
of the Raspberry Pi and adds the region used by the Trusted Firmware.

This system replaces the previous one consisting on adding
``memmap=16M$256M`` to the Linux command line. It's also meant to be
used by U-Boot and any other bootloader that understands DTB files.

Change-Id: I13ee528475fb043d6e8d9e9f24228e37ac3ac436
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #1643 from antonio-nino-diaz-arm/an/libfdt

Update libfdt to version 1.4.7

Merge pull request #1639 from chandnich/scmi-update

plat/arm/scmi: introduce plat_css_get_scmi_info API

juno: Increase BL2 max size

Version 1.4.7 of libfdt is bigger than the current one (1.4.2) and the
current reserved space for BL2 in Juno isn't enough to fit the Trusted
Firmware when compiling with

juno: Increase BL2 max size

Version 1.4.7 of libfdt is bigger than the current one (1.4.2) and the
current reserved space for BL2 in Juno isn't enough to fit the Trusted
Firmware when compiling with clang or armclang.

Change-Id: I7b73394ca60d17f417773f56dd5b3d54495a45a8
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #1648 from jforissier/qemu-dt-1M

qemu: increase PLAT_QEMU_DT_MAX_SIZE to 1 MiB

tzc: Fix MISRA defects

The definitions FAIL_CONTROL_*_SHIFT were incorrect, they have been
fixed.

The types tzc_region_attributes_t and tzc_action_t have been removed and
replaced by unsigned int b

tzc: Fix MISRA defects

The definitions FAIL_CONTROL_*_SHIFT were incorrect, they have been
fixed.

The types tzc_region_attributes_t and tzc_action_t have been removed and
replaced by unsigned int because it is not allowed to do logical
operations on enums.

Also, fix some address definitions in arm_def.h.

Change-Id: Id37941d76883f9fe5045a5f0a4224c133c504d8b
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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tools: Move doimage to marvell folder for future add-ons

Move doimage utility from toos/doimage to tools/marvell/doimage.
This is done for supporting mode Marvell tools in the future.

Signed-off-by

tools: Move doimage to marvell folder for future add-ons

Move doimage utility from toos/doimage to tools/marvell/doimage.
This is done for supporting mode Marvell tools in the future.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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allwinner: Use the arisc to turn off ARM cores

PSCI requires a core to turn itself off, which we can't do properly by
just executing an algorithm on that very core. As a consequence we just
put a co

allwinner: Use the arisc to turn off ARM cores

PSCI requires a core to turn itself off, which we can't do properly by
just executing an algorithm on that very core. As a consequence we just
put a core into WFI on CPU_OFF right now.
To fix this let's task the "arisc" management processor (an OpenRISC
core) with that task of asserting reset and turning off the core's power
domain. We use a handcrafted sequence of OpenRISC instructions to
achieve this, and hand this data over to the new sunxi_execute_arisc_code()
routine.
The commented source code for this routine is provided in a separate file,
but the ATF code contains the already encoded instructions as data.
The H6 uses the same algorithm, but differs in the MMIO addresses, so
provide a SoC (family) specific copy of that code.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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allwinner: Prepare for executing code on the management processor

The more recent Allwinner SoCs contain an OpenRISC management
controller (called arisc or CPUS), which shares the bus with the ARM c

allwinner: Prepare for executing code on the management processor

The more recent Allwinner SoCs contain an OpenRISC management
controller (called arisc or CPUS), which shares the bus with the ARM cores,
but runs on a separate power domain. This is meant to handle power
management with the ARM cores off.
There are efforts to run sophisticated firmware on that core
(communicating via SCPI with the ARM world), but for now can use it for
the rather simple task of helping to turn the ARM cores off. As this
cannot be done by ARM code itself (because execution stops at the
first of the three required steps), we can offload some instructions to
this management processor.
This introduces a helper function to hand over a bunch of instructions
and triggers execution. We introduce a bakery lock to avoid two cores
trying to use that (single) arisc core. The arisc code is expected to
put itself into reset after is has finished execution.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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allwinner: PMIC: AXP803: Delay activation of DC1SW switch

There are reports that activating the DC1SW before certain other
regulators leads to the PMIC overheating and consequently shutting down.
To

allwinner: PMIC: AXP803: Delay activation of DC1SW switch

There are reports that activating the DC1SW before certain other
regulators leads to the PMIC overheating and consequently shutting down.
To avoid this situation, delay the activation of the DC1SW line until
the very end, so those other lines are always activated earlier.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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allwinner: PMIC: AXP803: Setup basic voltage rails

Based on the just introduced PMIC FDT framework, we check the DT for more
voltage rails that need to be setup early:
- DCDC1 is typically the main

allwinner: PMIC: AXP803: Setup basic voltage rails

Based on the just introduced PMIC FDT framework, we check the DT for more
voltage rails that need to be setup early:
- DCDC1 is typically the main board power rail, used for I/O pins, for
instance. The PMIC's default is 3.0V, but 3.3V is what most boards use,
so this needs to be adjusted as soon as possible.
- DCDC5 is supposed to be connected to the DRAM. The AXP has some
configurable reset voltage, but some boards get that wrong, so we better
set up this here to avoid over- or under-volting.
- DLDO1,2,3 and FLDO1 mostly drive some graphics related IP, some boards
need this to be up to enable HDMI or the LCD screen, so we get screen
output in U-Boot.

To get the right setup, but still being flexible, we query the DT for
the required voltage and whether that regulator is actually used. That
gives us some robust default setup U-Boot is happy with.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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allwinner: Scan AXP803 FDT node to setup initial power rails

Now that we have a pointer to the device tree blob, let's use that to
do some initial setup of the PMIC:
- We scan the DT for the compati

allwinner: Scan AXP803 FDT node to setup initial power rails

Now that we have a pointer to the device tree blob, let's use that to
do some initial setup of the PMIC:
- We scan the DT for the compatible string to find the PMIC node.
- We switch the N_VBUSEN pin if the DT property tells us so.
- We scan over all regulator subnodes, and switch DC1SW if there is at
least one other node referencing it (judging by the existence of a
phandle property in that subnode).
This is just the first part of the setup, a follow up patch will setup
voltages.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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allwinner: Pass FDT address to sunxi_pmic_setup()

For Allwinner boards we now use some heuritistics to find a preloaded
.dtb file.

Pass this address on to the PMIC setup routine, so that it can use

allwinner: Pass FDT address to sunxi_pmic_setup()

For Allwinner boards we now use some heuritistics to find a preloaded
.dtb file.

Pass this address on to the PMIC setup routine, so that it can use the
information contained therein to setup some initial power rails.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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allwinner: Find DTB in BL33 image

The initial PMIC setup for the Allwinner platform is quite board
specific, and used to be guarded by reading the .dtb stub *name* from the
SPL image in the legacy A

allwinner: Find DTB in BL33 image

The initial PMIC setup for the Allwinner platform is quite board
specific, and used to be guarded by reading the .dtb stub *name* from the
SPL image in the legacy ATF port. This doesn't scale particularly well,
and requires constant maintainance.
Instead having the actual .dtb available would be much better, as the PMIC
setup requirements could be read from there directly.
The only available BL33 for Allwinner platforms so far is U-Boot, and
fortunately U-Boot comes with the full featured .dtb, appended to the
end of the U-Boot image.

Introduce some code that scans the beginning of the BL33 image to look
for the load address, which is followed by the image size. Adding those
two values together gives us the end of the image and thus the .dtb
address. Verify that this heuristic is valid by sanitising some values
and checking the DTB magic.

Print out the DTB address and the model name, if specified in the root
node.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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