Merge pull request #1772 from glneo/clear-proxy-queue

TI K3 Clear proxy receive queue on transmit

Merge pull request #1775 from glneo/uart-baud-rate

ti: k3: common: Allow customizing UART baud rate using build options

Merge pull request #1774 from glneo/error-message

ti: k3: drivers: sec_proxy: Switch error messages

Merge pull request #1771 from glneo/core-shutdown

TI K3 Core shutdown changes

SPM: Rename SPM_DEPRECATED flag to SPM_MM

The SPM implementation based on MM is going to be kept for the
foreseeable future.

Change-Id: I11e96778a4f52a1aa803e7e048d9a7cb24a53954
Signed-off-by: Anto

SPM: Rename SPM_DEPRECATED flag to SPM_MM

The SPM implementation based on MM is going to be kept for the
foreseeable future.

Change-Id: I11e96778a4f52a1aa803e7e048d9a7cb24a53954
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Acked-by: Sumit Garg <sumit.garg@linaro.org>

show more ...

ti: k3: common: Allow customizing UART baud rate using build options

To accommodate scenarios where we want to use a UART baud rate other than
the default 115,200 allow the associated compiler defin

ti: k3: common: Allow customizing UART baud rate using build options

To accommodate scenarios where we want to use a UART baud rate other than
the default 115,200 allow the associated compiler definition to be set
via the K3_USART_BAUD build option by updating the platform make file.

Since the platform make file now also contains the default value (still
115,200), go ahead and remove the redundant definition from the platform
header file.

Suggested-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>

show more ...

ti: k3: drivers: ti_sci: Clear receive queue before transmitting

Send and receive currently must be be serialized, any message already in
the receive queue when a new message is to be sent will caus

ti: k3: drivers: ti_sci: Clear receive queue before transmitting

Send and receive currently must be be serialized, any message already in
the receive queue when a new message is to be sent will cause a mismatch
with the expected response from this new message. Clear out all messages
from the response queue before sending a new request.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>

show more ...

ti: k3: drivers: sec_proxy: Allow clearing a Secure Proxy receive thread

It can be needed to discard all messages in a receive queue. This
can be used during some error recovery situations.

Signed-

ti: k3: drivers: sec_proxy: Allow clearing a Secure Proxy receive thread

It can be needed to discard all messages in a receive queue. This
can be used during some error recovery situations.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>

show more ...

ti: k3: common: Use shutdown API for PSCI core poweroff

To ensure WFI is reached before the PSC is trigger to power-down
a processor, the shutdonw API must be used.

Signed-off-by: Andrew F. Davis <

ti: k3: common: Use shutdown API for PSCI core poweroff

To ensure WFI is reached before the PSC is trigger to power-down
a processor, the shutdonw API must be used.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>

show more ...

ti: k3: drivers: ti_sci: Add processor shutdown API

This is a pseudo-API command consisting of a wait processor status
command and a set device state command queued back-to-back without
waiting for

ti: k3: drivers: ti_sci: Add processor shutdown API

This is a pseudo-API command consisting of a wait processor status
command and a set device state command queued back-to-back without
waiting for the System Firmware to ACK either message.

This is needed as the K3 power down specification states the System
Firmware must wait for a processor to be in WFI/WFE before powering
it down. The current implementation of System Firmware does not provide
such a command. Also given that with PSCI the core to be shutdown is the
core that is processing the shutdown request, the core cannot itself wait
for its own WFI/WFE status. To workaround this limitation, we submit
a wait processor status command followed by the actual shutdown command.
The shutdown command will not be processed until the wait command has
finished. In this way we can continue to WFI before the wait command
status has been met or timed-out and the shutdown command is processed.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>

show more ...

ti: k3: drivers: ti_sci: Add processor status wait API

This TI-SCI API can be used wait for a set of processor status flags to
be set or cleared. The flags are processor type specific. This command

ti: k3: drivers: ti_sci: Add processor status wait API

This TI-SCI API can be used wait for a set of processor status flags to
be set or cleared. The flags are processor type specific. This command
will not return ACK until the specified status is met. NACK will be
returned after the timeout elapses or on error.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>

show more ...

ti: k3: drivers: sec_proxy: Switch error messages

The logic is correct here, but the error messages are
reversed, switch them.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Nishanth Menon <

ti: k3: drivers: sec_proxy: Switch error messages

The logic is correct here, but the error messages are
reversed, switch them.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>

show more ...

Merge pull request #1764 from vwadekar/tf2.0-tegra-downstream-rebase-1.7.19

Tf2.0 tegra downstream rebase 1.7.19

Tegra: memctrl: clean MC INT status before exit to bootloader

This patch cleans the Memory controller's interrupt status
register, before exiting to the non-secure world during
cold boot. This is re

Tegra: memctrl: clean MC INT status before exit to bootloader

This patch cleans the Memory controller's interrupt status
register, before exiting to the non-secure world during
cold boot. This is required as we observed that the MC's
arbitration bit is set before exiting the secure world.

Change-Id: Iacd01994d03b3b9cbd7b8a57fe7ab5b04e607a9f
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>

show more ...

Tegra: use 'PLATFORM_MAX_CPUS_PER_CLUSTER' to calculate core position

This patch updates the plat_my_core_pos() and platform_get_core_pos() helper
functions to use the `PLATFORM_MAX_CPUS_PER_CLUSTER

Tegra: use 'PLATFORM_MAX_CPUS_PER_CLUSTER' to calculate core position

This patch updates the plat_my_core_pos() and platform_get_core_pos() helper
functions to use the `PLATFORM_MAX_CPUS_PER_CLUSTER` macro to calculate the
core position.

core_pos = CoreId + (ClusterId * PLATFORM_MAX_CPUS_PER_CLUSTER)

Change-Id: Ic49f2fc7ded23bf9484c8fe104025df8884b9faf
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra: memctrl_v2: pack TZDRAM base into SCRATCH54_LO

This patch moves the TZDRAM base address to SCRATCH55_LO due
to security concerns. The HI and LO address bits are packed
into SCRATCH55_LO for t

Tegra: memctrl_v2: pack TZDRAM base into SCRATCH54_LO

This patch moves the TZDRAM base address to SCRATCH55_LO due
to security concerns. The HI and LO address bits are packed
into SCRATCH55_LO for the warmboot firmware to restore.
SCRATCH54_HI is still being used for backward compatibility,
but would be removed eventually.

The scratch registers are populated as:
* RSV55_0 = CFG1[12:0] | CFG0[31:20]
* RSV55_1 = CFG3[1:0]
* RSV54_1 = CFG1[12:0]

Change-Id: Idc20d165d8117488010fcc8dfd946f7ad475da58
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>

show more ...

Tegra: bpmp: Increase timeout to 2ms

To deal with upcoming EMC periodic compensation, increase the BPMP timeout
to 2ms.

Change-Id: I8572c031168defd15504d905c4d625f44dd7fa3d
Signed-off-by: Peter De

Tegra: bpmp: Increase timeout to 2ms

To deal with upcoming EMC periodic compensation, increase the BPMP timeout
to 2ms.

Change-Id: I8572c031168defd15504d905c4d625f44dd7fa3d
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>

show more ...

Tegra: remove duplicate code from CPU's power on path

This patch removes duplicate code from the CPU's power on path. The removed
code is already present as part of PSCI's power on logic.

Change-Id

Tegra: remove duplicate code from CPU's power on path

This patch removes duplicate code from the CPU's power on path. The removed
code is already present as part of PSCI's power on logic.

Change-Id: I4d18a605b219570c6bf997b9e6be6e7853ebf5cd
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra: enable 'WARMBOOT_ENABLE_DCACHE_EARLY' flag

This patch enables the 'WARMBOOT_ENABLE_DCACHE_EARLY' flag to enable
D-cache early, during the CPU warmboot sequence. This flag is applicable
for pl

Tegra: enable 'WARMBOOT_ENABLE_DCACHE_EARLY' flag

This patch enables the 'WARMBOOT_ENABLE_DCACHE_EARLY' flag to enable
D-cache early, during the CPU warmboot sequence. This flag is applicable
for platforms like Tegra, which do not require interconnect programming to
enable cache coherency.

Change-Id: Id39471cf0922799960d8f1de6e5e0d605a53f7ca
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra210_B01: SC7: Select RNG mode based on ECID

If ECID is valid, we can use force instantiation
otherwise, we should use reseed for random data
generation for RNG operations in SE context save
DNI

Tegra210_B01: SC7: Select RNG mode based on ECID

If ECID is valid, we can use force instantiation
otherwise, we should use reseed for random data
generation for RNG operations in SE context save
DNI because we are not keeping software save
sequence in main.

Change-Id: I73d650e6f45db17b780834b8de4c10501e05c8f3
Signed-off-by: Samuel Payne <spayne@nvidia.com>

show more ...

Tegra: trusty: pass profiling base to Trusted OS

* Previous boot loader passes Shared DRAM address
to be used by Trusted OS to dump its boot timing records
* This patch adds support to pass the pa

Tegra: trusty: pass profiling base to Trusted OS

* Previous boot loader passes Shared DRAM address
to be used by Trusted OS to dump its boot timing records
* This patch adds support to pass the parameter
to Trusted OS during cold boot

Change-Id: I9f95bb6de80b1bbd2d2d6ec42619f895d911b8ed
Signed-off-by: Akshay Sharan <asharan@nvidia.com>

show more ...

Tegra210B01: SE/SE2 and PKA1 context save (SW)

This change ports the software based SE context save routines.
The software implements the context save sequence for SE/SE2 and
PKA1. The context save

Tegra210B01: SE/SE2 and PKA1 context save (SW)

This change ports the software based SE context save routines.
The software implements the context save sequence for SE/SE2 and
PKA1. The context save routine is intended to be invoked from
the ATF SC7 entry.

Change-Id: I9aa156d6e7e22a394bb10cb0c3b05fc303f08807
Signed-off-by: Marvin Hsu <marvinh@nvidia.com>

show more ...

Tegra: memctrl: assert if dynamic memmap fails

This patch adds an assert in case the dynamic memmap routine fails.

Change-Id: Idd20debbb8944340f5928c6f2cfea973a63a7b1c
Signed-off-by: Varun Wadekar

Tegra: memctrl: assert if dynamic memmap fails

This patch adds an assert in case the dynamic memmap routine fails.

Change-Id: Idd20debbb8944340f5928c6f2cfea973a63a7b1c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra: set PLAT_LOG_LEVEL_ASSERT macro to LOG_LEVEL_INFO

This patch enables prints from asserts() for release/debug builds
on all Tegra platforms.

Change-Id: Ie256437a325a7c5015a10f55aba2287a91b57b

Tegra: set PLAT_LOG_LEVEL_ASSERT macro to LOG_LEVEL_INFO

This patch enables prints from asserts() for release/debug builds
on all Tegra platforms.

Change-Id: Ie256437a325a7c5015a10f55aba2287a91b57bca
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra210: increase number of dynamic memory mappings

This patch increases the MAX_MMAP_REGIONS build flag to allow
Tegra210 platforms to dynamically map multiple memory apertures
at the same time. T

Tegra210: increase number of dynamic memory mappings

This patch increases the MAX_MMAP_REGIONS build flag to allow
Tegra210 platforms to dynamically map multiple memory apertures
at the same time. This takes care of scenarios when we get multiple
requests to memmap memory apertures at the same time.

Change-Id: If4fe23b454e7d588e35acfbf024b9ccbb3daccc7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...