| 7aba390f | 08-May-2017 |
Anthony Zhou <anzhou@nvidia.com> |
Tegra: topology: fix MISRA defects for Rule 4.6
This patch uses int32_t to replace ints, to fix Rule 4.6 of the
MISRA standard.
Change-Id: I20ac6185929eced684b43da3ef1f8cd5fbddc83d
Signed-off-by: A
Tegra: topology: fix MISRA defects for Rule 4.6
This patch uses int32_t to replace ints, to fix Rule 4.6 of the
MISRA standard.
Change-Id: I20ac6185929eced684b43da3ef1f8cd5fbddc83d
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 82e73ae7 | 08-May-2017 |
Anthony Zhou <anzhou@nvidia.com> |
Tegra: fiq_glue: fix MISRA defects for Rule 2.7
This patch adds (void) for unused function parameters to
fix Rule 2.7 of the MISRA standard.
Change-Id: Ibc3f10b3bfe73363383b4c28413ab8d99fbc8c89
Sig
Tegra: fiq_glue: fix MISRA defects for Rule 2.7
This patch adds (void) for unused function parameters to
fix Rule 2.7 of the MISRA standard.
Change-Id: Ibc3f10b3bfe73363383b4c28413ab8d99fbc8c89
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| ce3c97c9 | 11-Apr-2017 |
Marvin Hsu <marvinh@nvidia.com> |
Tegra210B01: SE1 and SE2/PKA1 context save (atomic)
This patch adds the implementation of the SE atomic context save
sequence. The atomic context-save consistently saves to the TZRAM
carveout; thus
Tegra210B01: SE1 and SE2/PKA1 context save (atomic)
This patch adds the implementation of the SE atomic context save
sequence. The atomic context-save consistently saves to the TZRAM
carveout; thus there is no need to declare context save buffer or
map MMU region in TZRAM for context save. The atomic context-save
routine is responsible to validate the context-save progress
counter, where CTX_SAVE_CNT=133(SE1)/646(SE2), and the SE error
status to ensure the context save procedure complete successfully.
Change-Id: Ic80843902af70e76415530266cb158f668976c42
Signed-off-by: Marvin Hsu <marvinh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 1d49112b | 01-Mar-2017 |
Anthony Zhou <anzhou@nvidia.com> |
Tegra: sip_calls: fix defects flagged by MISRA scan
Main fixes:
* Expressions resulting from the expansion of macro parameters
shall be enclosed in parentheses [Rule 20.7]
* Added explicit casts
Tegra: sip_calls: fix defects flagged by MISRA scan
Main fixes:
* Expressions resulting from the expansion of macro parameters
shall be enclosed in parentheses [Rule 20.7]
* Added explicit casts (e.g. 0U) to integers in order for them
to be compatible with whatever operation they're used in [Rule
10.1]
* Fix implicit widening of composite assignment [Rule 10.6]
Change-Id: Ia83c3ab6e4c8c03c19c950978a7936ebfc290590
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| b495791b | 23-Nov-2016 |
Harvey Hsieh <hhsieh@nvidia.com> |
Tegra: support to set the L2 ECC and Parity enable bit
This patch adds capability to read the boot flag to enable L2 ECC
and Parity Protection bit for the Cortex-A57 CPUs. The previous
bootloader se
Tegra: support to set the L2 ECC and Parity enable bit
This patch adds capability to read the boot flag to enable L2 ECC
and Parity Protection bit for the Cortex-A57 CPUs. The previous
bootloader sets this flag value for the platform.
* with some coverity fix:
MISRA C-2012 Directive 4.6
MISRA C-2012 Rule 2.5
MISRA C-2012 Rule 10.3
MISRA C-2012 Rule 10.4
Change-Id: Id7303bbbdc290b52919356c31625847b8904b073
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 322e7c3e | 10-Apr-2017 |
Harvey Hsieh <hhsieh@nvidia.com> |
Tegra: console clock settings for real/FPGA platforms
This patch sets up the clock for the UART console, for real Silicon
and FPGA platforms. FPGA platforms run the UART clock source at
13MHz, where
Tegra: console clock settings for real/FPGA platforms
This patch sets up the clock for the UART console, for real Silicon
and FPGA platforms. FPGA platforms run the UART clock source at
13MHz, whereas the clock cource runs at 408MHz for real silicon.
Change-Id: Ibfd99df032ec473f29e636e597cfc95a0f580598
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| d3b71331 | 12-Apr-2017 |
Marvin Hsu <marvinh@nvidia.com> |
Tegra: platform: helper functions to read chip ID
This patch adds helper functions to find out the chip ID of the
Tegra SoC.
Change-Id: Ia3901dc7cdf77d8c23884d1ed38a80dba6a8afde
Signed-off-by: Marv
Tegra: platform: helper functions to read chip ID
This patch adds helper functions to find out the chip ID of the
Tegra SoC.
Change-Id: Ia3901dc7cdf77d8c23884d1ed38a80dba6a8afde
Signed-off-by: Marvin Hsu <marvinh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 7b3b41d6 | 28-Apr-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: retrieve power domain tree from the platforms
The platform code generates the power domain tree. The handler to
retrieve the tree should also reside in the platform code.
This patch moves th
Tegra: retrieve power domain tree from the platforms
The platform code generates the power domain tree. The handler to
retrieve the tree should also reside in the platform code.
This patch moves the plat_get_power_domain_tree_desc() to the
individual platforms.
Change-Id: Iaafc83ed381d83129501111ef655e3c58a8a553f
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| c62be079 | 22-Mar-2017 |
Anthony Zhou <anzhou@nvidia.com> |
Tegra: platform: support simulation platforms and MISRA fixes
This patch adds support for simulation platforms as well as
fixes issues flagged by the MISRA scans.
Main MISRA fixes:
* Added explici
Tegra: platform: support simulation platforms and MISRA fixes
This patch adds support for simulation platforms as well as
fixes issues flagged by the MISRA scans.
Main MISRA fixes:
* Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]
* Fix return type doesn't match the function type [Rule 10.3]
* Use single return point instead of multiple [Rule 15.5]
* Change return type for the tegra_platform_is_x handlers to bool
Change-Id: I871b7c37b22942f6c0c2049c14cc626d4a24d81c
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| cd1f39b4 | 16-Jan-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge pull request #1738 from ardbiesheuvel/synquacer-spm
synquacer: add SPM support |
| edcb50ab | 16-Jan-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1757 from antonio-nino-diaz-arm/an/includes
Move BL1 and BL2 private defines to bl_common.h |
| f6b79544 | 16-Jan-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1755 from Anson-Huang/lpuart
make lpuart and imx uart work for debug mode |
| 8013bb57 | 16-Jan-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1758 from pbeesley-arm/pb/spelling
Correct typographical errors |
| 434454a2 | 29-Dec-2018 |
Ard Biesheuvel <ard.biesheuvel@linaro.org> |
plat/synquacer: enable SPM support
Enable the deprecated SPM framework for the SynQuacer platform.
It involves creating a memory layout in secure DRAM, and wiring
up the SPM infrastructure so that t
plat/synquacer: enable SPM support
Enable the deprecated SPM framework for the SynQuacer platform.
It involves creating a memory layout in secure DRAM, and wiring
up the SPM infrastructure so that the secure partition payload
that is loaded into this region by the SCP firmware is dispatched
appropriately.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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|
| e373b6a2 | 29-Dec-2018 |
Ard Biesheuvel <ard.biesheuvel@linaro.org> |
plat/synquacer: enable OP-TEE logic only if SPD_opteed is set
The logic that initializes the BL32 entry point data structure
should only be executed if we are in fact loading OP-TEE, and
not if BL32
plat/synquacer: enable OP-TEE logic only if SPD_opteed is set
The logic that initializes the BL32 entry point data structure
should only be executed if we are in fact loading OP-TEE, and
not if BL32_BASE is set for other reasons (i.e., when enabling
SPM)
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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|
| 8aabea33 | 11-Jan-2019 |
Paul Beesley <paul.beesley@arm.com> |
Correct typographical errors
Corrects typos in core code, documentation files, drivers, Arm
platforms and services.
None of the corrections affect code; changes are limited to comments
and other do
Correct typographical errors
Corrects typos in core code, documentation files, drivers, Arm
platforms and services.
None of the corrections affect code; changes are limited to comments
and other documentation.
Change-Id: I5c1027b06ef149864f315ccc0ea473e2a16bfd1d
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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|
| 234bc7f8 | 15-Jan-2019 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
plat/arm: Fix header dependencies
From now on, platform_def.h must include any header with definitions that
are platform-specific (like arm_def.h) and the included headers mustn't
include back platf
plat/arm: Fix header dependencies
From now on, platform_def.h must include any header with definitions that
are platform-specific (like arm_def.h) and the included headers mustn't
include back platform_def.h, and shouldn't be used by other files. Only
platform_def.h should be included in other files. This will ensure that all
needed definitions are present, rather than needing to include all the
headers in all the definitions' headers just in case.
This also prevents problems like cyclic dependencies.
Change-Id: I9d3cf4d1de4b956fa035c79545222697acdaf5ca
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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|
| c9f9d9ea | 18-Dec-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Move BL1 and BL2 private defines to bl_common.h
The definitions in bl1/bl1_private.h and bl2/bl2_private.h are useful for
platforms that may need to access them.
Change-Id: Ifd1880f855ddafcb3bfcaf1
Move BL1 and BL2 private defines to bl_common.h
The definitions in bl1/bl1_private.h and bl2/bl2_private.h are useful for
platforms that may need to access them.
Change-Id: Ifd1880f855ddafcb3bfcaf1ed4a4e0f121eda174
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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|
| 2e8ab4f5 | 15-Jan-2019 |
Anson Huang <Anson.Huang@nxp.com> |
imx: make imx uart work for debug mode
With DEBUG_CONSOLE enabled, build will fail for imx8mq platform:
./build/imx8mq/release/bl31/imx8mq_bl31_setup.o:
In function `bl31_early_platform_setup2':
im
imx: make imx uart work for debug mode
With DEBUG_CONSOLE enabled, build will fail for imx8mq platform:
./build/imx8mq/release/bl31/imx8mq_bl31_setup.o:
In function `bl31_early_platform_setup2':
imx8mq_bl31_setup.c:(.text.bl31_early_platform_setup2+0x40):
undefined reference to `console_uart_register'
Makefile:741: recipe for target 'build/imx8mq/release/bl31/bl31.elf' failed
make: *** [build/imx8mq/release/bl31/bl31.elf] Error 1
Besides, the .console_flush callback needs to be added to avoid
panic when debug mode is enabled, since the console_flush() will
call it without checking whether the function callback is valid.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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|
| f1ac7964 | 15-Jan-2019 |
Anson Huang <Anson.Huang@nxp.com> |
imx: add necessary lpuart console_flush callback for debug
Current lpuart driver does NOT implement .console_flush callback,
if debug console is enabled, the console_flush() will call the
undefined
imx: add necessary lpuart console_flush callback for debug
Current lpuart driver does NOT implement .console_flush callback,
if debug console is enabled, the console_flush() will call the
undefined .console_flush callback(NULL) for lpuart and leak to
panic, this patch adds .console_flush callback to make lpuart work
for debug mode.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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|
| 12e0ca46 | 27-Dec-2018 |
Joel Hutton <Joel.Hutton@Arm.com> |
hikey960:Corrected erroneous DDR_SIZE
Change-Id: I7194a9a5f0e41308eb3242d20c0d3434f72da591
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com> |
| f58c3100 | 28-Nov-2018 |
Joel Hutton <Joel.Hutton@Arm.com> |
hikey960: Increase max xlat tables
It is cleaner to use the same number of tables regardless of whether
OP-TEE is used or not. This doesn't result in a significant memory
usage increase.
Change-Id:
hikey960: Increase max xlat tables
It is cleaner to use the same number of tables regardless of whether
OP-TEE is used or not. This doesn't result in a significant memory
usage increase.
Change-Id: I38bcaa3f2f197c0a352153117592749f189a265c
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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|
| 65c80d60 | 09-Jan-2019 |
Jolly Shah <jollys@xilinx.com> |
xilinx: Move IPI functions to common file
pm_service ipi functions can be used by other xilinx
platforms. So move it to common directory. Also change
node_id member type in pm_proc structure so it c
xilinx: Move IPI functions to common file
pm_service ipi functions can be used by other xilinx
platforms. So move it to common directory. Also change
node_id member type in pm_proc structure so it can be
used for versal where device IDs are used instead of
node IDs.
To accommodate this change header files are re-organized.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
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|
| 5bd029bc | 07-Jan-2019 |
Jolly Shah <jollys@xilinx.com> |
xilinx: pm_service: Rename macros to use generic macro names
ZynqMP pm_service ipi file uses platform specific macros names.
pm_service ipi functions can be used by other Xilinx platforms
also. Make
xilinx: pm_service: Rename macros to use generic macro names
ZynqMP pm_service ipi file uses platform specific macros names.
pm_service ipi functions can be used by other Xilinx platforms
also. Make rename macros to use generic names so that it can be
used by common file.
pm_service ipi functions will be moved to common file in next patch.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
show more ...
|
| 28e4d370 | 07-Jan-2019 |
Jolly Shah <jollys@xilinx.com> |
xilinx: zynqmp: Rename pm_api members to use generic name
Use generic name for pm_api structure member, so that pm_api
structure can be used other Xilinx platforms.
Structure definition will be mov
xilinx: zynqmp: Rename pm_api members to use generic name
Use generic name for pm_api structure member, so that pm_api
structure can be used other Xilinx platforms.
Structure definition will be moved to common file in upcoming
patch.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
show more ...
|