| 40fac1ab | 23-Aug-2019 |
Carlo Caione <ccaione@baylibre.com> |
amlogic: Move assembly helpers to common directory
The assembly helpers are common to all the amlogic SoCs. Move the .S
file to the common directory.
Signed-off-by: Carlo Caione <ccaione@baylibre.c
amlogic: Move assembly helpers to common directory
The assembly helpers are common to all the amlogic SoCs. Move the .S
file to the common directory.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I0d8616a7ae22dbcb14848cefd0149b6bb5814ea6
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| 1b250198 | 23-Aug-2019 |
Carlo Caione <ccaione@baylibre.com> |
amlogic: Introduce directory parameters in the makefiles
Make the platform name a parameter for the source directories. Besides a
cosmetic fix, this is going to be helpful when reusing the same Make
amlogic: Introduce directory parameters in the makefiles
Make the platform name a parameter for the source directories. Besides a
cosmetic fix, this is going to be helpful when reusing the same Makefile
for different SoCs.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I307897a21800cca8ad68a5ab8972d27e9356ff2a
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| 4a079c75 | 23-Aug-2019 |
Carlo Caione <ccaione@baylibre.com> |
meson: Rename platform directory to amlogic
Meson is the internal code name for the SoC family. The correct name for
the platform should be Amlogic. Change the name of the platform
directory.
Signe
meson: Rename platform directory to amlogic
Meson is the internal code name for the SoC family. The correct name for
the platform should be Amlogic. Change the name of the platform
directory.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Icc140e1ea137f12117acbf64c7dcb1a8b66b345d
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| 5dbdf8e4 | 05-Sep-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "intel: stratix10: Fix reliance on hard coded clock information" into integration |
| abfd5719 | 23-Jul-2019 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
uniphier: set CONSOLE_FLAG_TRANSLATE_CRLF and clean up console driver
This console driver sends '\r' before 'n', not after.
It works, but the convention is "\r\n" (i.e. CRLF)
Instead of fixing it i
uniphier: set CONSOLE_FLAG_TRANSLATE_CRLF and clean up console driver
This console driver sends '\r' before 'n', not after.
It works, but the convention is "\r\n" (i.e. CRLF)
Instead of fixing it in the driver, set CONSOLE_FLAG_TRANSLATE_CRLF
to leave it to the framework.
Change-Id: I2154e29313739a40dff70cfb5c0f8989136d4ad2
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| 1e919529 | 19-Apr-2019 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: move check_header() to common code
This function can be used on several stm32mp devices, it is then moved in
plat/st/common/stm32mp_common.c.
Change-Id: I862debe39604410f71a9ddc2871302636
stm32mp1: move check_header() to common code
This function can be used on several stm32mp devices, it is then moved in
plat/st/common/stm32mp_common.c.
Change-Id: I862debe39604410f71a9ddc28713026362e9ecda
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 083bca22 | 24-Apr-2019 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: keep console during runtime
The runtime console is only kept in DEBUG configuration.
Change-Id: I0447dfcacb9a63a12bcdab7c55584d70c3220e5b
Signed-off-by: Yann Gautier <yann.gautier@st.com> |
| 02f5d820 | 11-Jul-2019 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: sp_min: initialize MMU and cache earlier
This change enhances performance and security in BL32 stage.
Change-Id: I64df5995fc6b04f6cf42d6a00a6d3d0f602b5407
Signed-off-by: Yann Gautier <yan
stm32mp1: sp_min: initialize MMU and cache earlier
This change enhances performance and security in BL32 stage.
Change-Id: I64df5995fc6b04f6cf42d6a00a6d3d0f602b5407
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 4b549b21 | 16-Apr-2019 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: add support for LpDDR3
This change enables LpDDR3 initialization with PMIC.
Change-Id: I2409a808335dfacd69a8517cb8510cee98bb8161
Signed-off-by: Yann Gautier <yann.gautier@st.com> |
| e463d3f4 | 22-May-2019 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: use a common function to check spinlock is available
To use spinlocks, MMU should be enabled, as well as data cache.
A common function is created (moved from clock file).
It is then used w
stm32mp1: use a common function to check spinlock is available
To use spinlocks, MMU should be enabled, as well as data cache.
A common function is created (moved from clock file).
It is then used whenever a spinlock has to be taken, in BSEC and clock
drivers.
Change-Id: I94baed0114a2061ad71bd5287a91bf7f1c6821f6
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| b2182cde | 04-Jun-2019 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: check if the SoC is single core
Among the variants of STM32MP, the STM32MP151 is a single Cortex-A7 chip.
A function is added to check the part number of the SoC.
If it corresponds to STM3
stm32mp1: check if the SoC is single core
Among the variants of STM32MP, the STM32MP151 is a single Cortex-A7 chip.
A function is added to check the part number of the SoC.
If it corresponds to STM32MP151A or STM32MP151C, then the chip has a single
Cortex-A7.
Change-Id: Icac2015c5d03ce0bcb8e99bbaf1ec8ada34be49c
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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| 10e7a9e9 | 13-May-2019 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: print information about board
On STMicroelectronics boards, the board information is stored in OTP.
This OTP is described in device tree, in BSEC board_id node.
Change-Id: Ieccbdcb0483436
stm32mp1: print information about board
On STMicroelectronics boards, the board information is stored in OTP.
This OTP is described in device tree, in BSEC board_id node.
Change-Id: Ieccbdcb048343680faac8dc577b75c67ac106f5b
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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| dec286dd | 04-Jun-2019 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: print information about SoC
This information is located in DBGMCU registers.
Change-Id: I480aa046fed9992e3d9665b1f0520bc4b6cfdf30
Signed-off-by: Yann Gautier <yann.gautier@st.com> |
| 73680c23 | 04-Jun-2019 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: add watchdog support
Introduce driver for STM32 IWDG peripheral (Independent Watchdog).
It is configured according to device tree content and should be enabled
from there.
The watchdog is
stm32mp1: add watchdog support
Introduce driver for STM32 IWDG peripheral (Independent Watchdog).
It is configured according to device tree content and should be enabled
from there.
The watchdog is not started by default. It can be started after an HW
reset if the dedicated OTP is fused.
The watchdog also needs to be frozen if a debugger is attached.
This is done by configuring the correct bits in DBGMCU.
This configuration is allowed by checking BSEC properties.
An increase of BL2 size is also required when adding this new code.
Change-Id: Ide7535d717885ce2f9c387cf17afd8b5607f3e7f
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
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| f12039be | 07-Aug-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
rcar_get3: drivers: ddr: Partly unify register macros between DDR A and B
The ddr_a and ddr_b register macros are the same for the most part,
unify them into a single header.
Signed-off-by: Marek V
rcar_get3: drivers: ddr: Partly unify register macros between DDR A and B
The ddr_a and ddr_b register macros are the same for the most part,
unify them into a single header.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I8f55d6d779837215339ac0010e8c8ab5f6748d75
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| 40c711a3 | 07-Aug-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
rcar_get3: drivers: ddr: Clean up common code
Do minor coding style changes to the common DDR init code to make it
checkpatch compliant and move macros out into rcar_def.h.
Signed-off-by: Marek Vas
rcar_get3: drivers: ddr: Clean up common code
Do minor coding style changes to the common DDR init code to make it
checkpatch compliant and move macros out into rcar_def.h.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I67eadf8099e4ff8702105c9e07b13f308d9dbe3d
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| 3441952f | 28-Aug-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge "intel: agilex: Clear PLL lostlock bypass mode" into integration |
| de580488 | 27-Aug-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "tegra: add support for multi console interface" into integration |
| 44e8d5eb | 20-Aug-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge "plat/arm: Introduce corstone700 platform." into integration |
| 7cc287de | 20-Aug-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge "rcar_gen3: plat: Rename RCAR_PRODUCT_* to PRR_PRODUCT_*" into integration |
| 7bdc4698 | 28-Nov-2018 |
Manish Pandey <manish.pandey2@arm.com> |
plat/arm: Introduce corstone700 platform.
This patch adds support for Corstone-700 foundation IP, which integrates
both Cortex-M0+ and Cortex-A(Host) processors in one handy, flexible
subsystem.
Thi
plat/arm: Introduce corstone700 platform.
This patch adds support for Corstone-700 foundation IP, which integrates
both Cortex-M0+ and Cortex-A(Host) processors in one handy, flexible
subsystem.
This is an example implementation of Corstone-700 IP host firmware.
Cortex-M0+ will take care of boot stages 1 and 2(BL1/BL2) as well as
bringing Host out RESET. Host will start execution directly from BL32 and
then will jump to Linux.
It is an initial port and additional features are expected to be added
later.
Change-Id: I7b5c0278243d574284b777b2408375d007a7736e
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
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| 44f4bb24 | 20-Aug-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge "rcar_gen3: plat: Factor out PRR_ macros into rcar_def.h" into integration |
| bfc0c079 | 20-Aug-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge "intel: agilex: HMC driver calculate DDR size" into integration |
| c3db45fb | 20-Aug-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge "console: add a flag to prepend '\r' in the multi-console framework" into integration |
| 24d16a2e | 16-Aug-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: agilex: HMC driver calculate DDR size
Driver will calculate DDR size instead of using hardcoded value
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I64
intel: agilex: HMC driver calculate DDR size
Driver will calculate DDR size instead of using hardcoded value
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I642cf2180929965ef12bd5ae4393b2f3d0dcddde
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