| 2d431df8 | 03-Feb-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
uniphier: make pinmon base address configurable
The register base will be changed in the next SoC. Make it
configurable.
Change-Id: I9fbb6bdd1cf06207618742d4ad7970d911c9bc26
Signed-off-by: Masahiro
uniphier: make pinmon base address configurable
The register base will be changed in the next SoC. Make it
configurable.
Change-Id: I9fbb6bdd1cf06207618742d4ad7970d911c9bc26
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| bda9cd70 | 03-Feb-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
uniphier: make NAND controller base address configurable
The next SoC does not support the NAND controller, but make the base
address configurable for consistency and future proof.
Change-Id: I776e
uniphier: make NAND controller base address configurable
The next SoC does not support the NAND controller, but make the base
address configurable for consistency and future proof.
Change-Id: I776e43ff2b0408577919b0b72849c3e1e5ce0758
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| 070dcbf5 | 03-Feb-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
uniphier: make eMMC controller base address configurable
The next SoC supports the same eMMC controller, but the register
base will be changed. Make it configurable.
Change-Id: I00cb5531bc3d8d49357
uniphier: make eMMC controller base address configurable
The next SoC supports the same eMMC controller, but the register
base will be changed. Make it configurable.
Change-Id: I00cb5531bc3d8d49357ad5e922cdd3d785355edf
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| 21c4f56f | 11-Feb-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "lm/fconf" into integration
* changes:
arm-io: Panic in case of io setup failure
MISRA fix: Use boolean essential type
fconf: Add documentation
fconf: Move platform
Merge changes from topic "lm/fconf" into integration
* changes:
arm-io: Panic in case of io setup failure
MISRA fix: Use boolean essential type
fconf: Add documentation
fconf: Move platform io policies into fconf
fconf: Add mbedtls shared heap as property
fconf: Add TBBR disable_authentication property
fconf: Add dynamic config DTBs info as property
fconf: Populate properties from dtb during bl2 setup
fconf: Load config dtb from bl1
fconf: initial commit
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| 698e231d | 11-Feb-2020 |
Max Shvetsov <maksims.svecovs@arm.com> |
Fixes ROTPK hash generation for ECDSA encryption
Forced hash generation used to always generate hash via RSA encryption.
This patch changes encryption based on ARM_ROTPK_LOCATION.
Also removes setti
Fixes ROTPK hash generation for ECDSA encryption
Forced hash generation used to always generate hash via RSA encryption.
This patch changes encryption based on ARM_ROTPK_LOCATION.
Also removes setting KEY_ALG based on ARM_ROTPL_LOCATION - there is no
relation between these two.
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: Id727d2ed06176a243719fd0adfa0cae26c325005
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| 63aa4094 | 11-Feb-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "spmd" into integration
* changes:
SPMD: enable SPM dispatcher support
SPMD: hook SPMD into standard services framework
SPMD: add SPM dispatcher based upon SPCI Beta 0
Merge changes from topic "spmd" into integration
* changes:
SPMD: enable SPM dispatcher support
SPMD: hook SPMD into standard services framework
SPMD: add SPM dispatcher based upon SPCI Beta 0 spec
SPMD: add support to run BL32 in TDRAM and BL31 in secure DRAM on Arm FVP
SPMD: add support for an example SPM core manifest
SPMD: add SPCI Beta 0 specification header file
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| 513b6165 | 10-Feb-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "coverity: Fix MISRA null pointer violations" into integration |
| ea25ce90 | 10-Feb-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fvp: Slightly Bump the stack size for bl1 and bl2" into integration |
| 65f6c3e9 | 10-Feb-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "amlogic/axg" into integration
* changes:
amlogic: axg: Add a build flag when using ATOS as BL32
amlogic: axg: Add support for the A113D (AXG) platform |
| c3fb00d9 | 11-Oct-2019 |
Achin Gupta <achin.gupta@arm.com> |
SPMD: enable SPM dispatcher support
This patch adds support to the build system to include support for the SPM
dispatcher when the SPD configuration option is spmd.
Signed-off-by: Achin Gupta <achi
SPMD: enable SPM dispatcher support
This patch adds support to the build system to include support for the SPM
dispatcher when the SPD configuration option is spmd.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
Change-Id: Ic1ae50ecd7403fcbcf1d318abdbd6ebdc642f732
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| 64758c97 | 11-Oct-2019 |
Achin Gupta <achin.gupta@arm.com> |
SPMD: add support to run BL32 in TDRAM and BL31 in secure DRAM on Arm FVP
This patch reserves and maps the Trusted DRAM for SPM core execution.
It also configures the TrustZone address space control
SPMD: add support to run BL32 in TDRAM and BL31 in secure DRAM on Arm FVP
This patch reserves and maps the Trusted DRAM for SPM core execution.
It also configures the TrustZone address space controller to run BL31
in secure DRAM.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
Change-Id: I7e1bb3bbc61a0fec6a9cb595964ff553620c21dc
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|
| 0cb64d01 | 11-Oct-2019 |
Achin Gupta <achin.gupta@arm.com> |
SPMD: add support for an example SPM core manifest
This patch repurposes the TOS FW configuration file as the manifest for
the SPM core component which will reside at the secure EL adjacent to
EL3.
SPMD: add support for an example SPM core manifest
This patch repurposes the TOS FW configuration file as the manifest for
the SPM core component which will reside at the secure EL adjacent to
EL3. The SPM dispatcher component will use the manifest to determine how
the core component must be initialised. Routines and data structure to
parse the manifest have also been added.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
Change-Id: Id94f8ece43b4e05609f0a1d364708a912f6203cb
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| d232ca5f | 10-Feb-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topics "rddaniel", "rdn1edge_dual" into integration
* changes:
plat/arm: add board support for rd-daniel platform
plat/arm/sgi: move GIC related constants to board files
pla
Merge changes from topics "rddaniel", "rdn1edge_dual" into integration
* changes:
plat/arm: add board support for rd-daniel platform
plat/arm/sgi: move GIC related constants to board files
platform/arm/sgi: add multi-chip mode parameter in HW_CONFIG dts
board/rdn1edge: add support for dual-chip configuration
drivers/arm/scmi: allow use of multiple SCMI channels
drivers/mhu: derive doorbell base address
plat/arm/sgi: include AFF3 affinity in core position calculation
plat/arm/sgi: add macros for remote chip device region
plat/arm/sgi: add chip_id and multi_chip_mode to platform variant info
plat/arm/sgi: move bl31_platform_setup to board file
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|
| 1f6b06c8 | 10-Feb-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "intel: Include address range check for SiP Mailbox" into integration |
| aab154fb | 07-Feb-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "qemu: define ARMV7_SUPPORTS_VFP" into integration |
| 2103a73b | 21-Jul-2019 |
Aditya Angadi <aditya.angadi@arm.com> |
plat/arm: add board support for rd-daniel platform
Add the initial board support for RD-Daniel Config-M platform.
Change-Id: I36df16c745bfe4bc817e275ad4722e5de57733cd
Signed-off-by: Jagadeesh Ujja
plat/arm: add board support for rd-daniel platform
Add the initial board support for RD-Daniel Config-M platform.
Change-Id: I36df16c745bfe4bc817e275ad4722e5de57733cd
Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com>
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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|
| 4e950109 | 29-Jan-2020 |
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> |
board/rde1edge: fix incorrect topology tree description
RD-E1-Edge platform consists of two clusters with eight CPUs each and
two processing elements (PE) per CPU. Commit a9fbf13e049e (plat/arm/sgi:
board/rde1edge: fix incorrect topology tree description
RD-E1-Edge platform consists of two clusters with eight CPUs each and
two processing elements (PE) per CPU. Commit a9fbf13e049e (plat/arm/sgi:
move topology information to board folder) defined the RD-E1-Edge
topology tree to have two clusters with eight CPUs each but PE per CPU
entries were not added. This patch fixes the topology tree accordingly.
Change-Id: I7f97f0013be60e5d51c214fce3962e246bae8a0b
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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|
| fe2293df | 03-Feb-2020 |
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> |
plat/arm/sgi: move GIC related constants to board files
In preparation for adding support for Reference Design platforms
which have different base addresses for GIC Distributor or
Redistributor, mov
plat/arm/sgi: move GIC related constants to board files
In preparation for adding support for Reference Design platforms
which have different base addresses for GIC Distributor or
Redistributor, move GIC related base addresses to individual platform
definition files.
Change-Id: Iecf52b4392a30b86905e1cd047c0ff87d59d0191
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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|
| 4d37aa76 | 26-Dec-2019 |
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> |
plat/arm/sgi: introduce number of chips macro
Introduce macro 'CSS_SGI_CHIP_COUNT' to allow Arm CSS platforms with
multi-chip support to define number of chiplets on the platform. By
default, this f
plat/arm/sgi: introduce number of chips macro
Introduce macro 'CSS_SGI_CHIP_COUNT' to allow Arm CSS platforms with
multi-chip support to define number of chiplets on the platform. By
default, this flag is set to 1 and does not affect the existing single
chip platforms.
For multi-chip platforms, override the default value of
CSS_SGI_CHIP_COUNT with the number of chiplets supported on the
platform. As an example, the command below sets the number of chiplets
to two on the RD-N1-Edge multi-chip platform:
export CROSS_COMPILE=<path-to-cross-compiler>
make PLAT=rdn1edge CSS_SGI_CHIP_COUNT=2 ARCH=aarch64 all
Change-Id: If364dc36bd34b30cc356f74b3e97633933e6c8ee
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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| 2bd5dcb9 | 30-Oct-2019 |
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> |
platform/arm/sgi: add multi-chip mode parameter in HW_CONFIG dts
Include multi-chip-mode parameter in HW_CONFIG dts to let next stage of
boot firmware know about the multi-chip operation mode.
Chan
platform/arm/sgi: add multi-chip mode parameter in HW_CONFIG dts
Include multi-chip-mode parameter in HW_CONFIG dts to let next stage of
boot firmware know about the multi-chip operation mode.
Change-Id: Ic7535c2280fd57180ad14aa0ae277cf0c4d1337b
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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|
| 2d4b719c | 28-Oct-2019 |
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> |
board/rdn1edge: add support for dual-chip configuration
RD-N1-Edge based platforms can operate in dual-chip configuration
wherein two rdn1edge SoCs are connected through a high speed coherent
CCIX l
board/rdn1edge: add support for dual-chip configuration
RD-N1-Edge based platforms can operate in dual-chip configuration
wherein two rdn1edge SoCs are connected through a high speed coherent
CCIX link.
This patch adds a function to check if the RD-N1-Edge platform is
operating in multi-chip mode by reading the SID register's NODE_ID
value. If operating in multi-chip mode, initialize GIC-600 multi-chip
operation by overriding the default GICR frames with array of GICR
frames and setting the chip 0 as routing table owner.
The address space of the second RD-N1-Edge chip (chip 1) starts from the
address 4TB. So increase the physical and virtual address space size to
43 bits to accommodate the multi-chip configuration. If the multi-chip
mode configuration is detected, dynamically add mmap entry for the
peripherals memory region of the second RD-N1-Edge SoC. This is required
to let the BL31 platform setup stage to configure the devices in the
second chip.
PLATFORM_CORE_COUNT macro is set to be multiple of CSS_SGI_CHIP_COUNT
and topology changes are added to represent the dual-chip configuration.
In order the build the dual-chip platform, CSS_SGI_CHIP_COUNT macro
should be set to 2:
export CROSS_COMPILE=<path-to-cross-compiler>
make PLAT=rdn1edge CSS_SGI_CHIP_COUNT=2 ARCH=aarch64 all
Change-Id: I576cdaf71f0b0e41b9a9181fa4feb7091f8c7bb4
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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| 31e703f9 | 31-Dec-2019 |
Aditya Angadi <aditya.angadi@arm.com> |
drivers/arm/scmi: allow use of multiple SCMI channels
On systems that have multiple platform components that can interpret the
SCMI messages, there is a need to support multiple SCMI channels (one
e
drivers/arm/scmi: allow use of multiple SCMI channels
On systems that have multiple platform components that can interpret the
SCMI messages, there is a need to support multiple SCMI channels (one
each to those platform components). Extend the existing SCMI interface
that currently supports only a single SCMI channel to support multiple
SCMI channels.
Change-Id: Ice4062475b903aef3b5e5bc37df364c9778a62c5
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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| f8931606 | 31-Dec-2019 |
Aditya Angadi <aditya.angadi@arm.com> |
drivers/mhu: derive doorbell base address
In order to allow the MHUv2 driver to be usable with multiple MHUv2
controllers, use the base address of the controller from the platform
information instea
drivers/mhu: derive doorbell base address
In order to allow the MHUv2 driver to be usable with multiple MHUv2
controllers, use the base address of the controller from the platform
information instead of the MHUV2_BASE_ADDR macro.
Change-Id: I4dbab87b929fb0568935e6c8b339ce67937f8cd1
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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| 80151c27 | 29-Oct-2019 |
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> |
plat/arm/sgi: include AFF3 affinity in core position calculation
AFF3 bits of MPIDR corresponds to Chip-Id in Arm multi-chip platforms.
For calculating linear core position of CPU cores from slave c
plat/arm/sgi: include AFF3 affinity in core position calculation
AFF3 bits of MPIDR corresponds to Chip-Id in Arm multi-chip platforms.
For calculating linear core position of CPU cores from slave chips, AFF3
bits has to be used. Update `plat_arm_calc_core_pos` assembly function
to include AFF3 bits in calculation.
Change-Id: I4af2bd82ab8e31e18bc61de22705a73893954260
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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| e4854153 | 28-Oct-2019 |
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> |
plat/arm/sgi: add macros for remote chip device region
Some of the Reference Design platforms like RD-N1-Edge can operate in
multi-chip configuration wherein two or more SoCs are connected through
a
plat/arm/sgi: add macros for remote chip device region
Some of the Reference Design platforms like RD-N1-Edge can operate in
multi-chip configuration wherein two or more SoCs are connected through
a high speed coherent CCIX link. For the RD platforms, the remote chip
address space is at the offset of 4TB per chip. In order for the primary
chip to access the device memory region on the remote chip, the required
memory region entries need to be added as mmap entry. This patch adds
macros related to the remote chip device memory region.
Change-Id: I833810b96f1a0e7c3c289ac32597b6ba03344c80
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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|