Tegra210: secure PMC hardware block

This patch sets the "secure" bit to mark the PMC hardware block
as accessible only from the secure world. This setting must be
programmed during cold boot and Sys

Tegra210: secure PMC hardware block

This patch sets the "secure" bit to mark the PMC hardware block
as accessible only from the secure world. This setting must be
programmed during cold boot and System Resume.

The sc7entry-fw, running on the COP, needs access to the PMC block
to enter System Suspend state, so "unlock" the PMC block before
passing control to the COP.

Change-Id: I00e39a49ae6b9f8c8eafe0cf7ff63fe6a67fdccf
Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>

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Tegra: delay_timer: support for physical secure timer

This patch modifies the delay timer driver to switch to the ARM
secure physical timer instead of using Tegra's on-chip uS timer.

The secure tim

Tegra: delay_timer: support for physical secure timer

This patch modifies the delay timer driver to switch to the ARM
secure physical timer instead of using Tegra's on-chip uS timer.

The secure timer is not accessible to the NS world and so eliminates
an important attack vector, where the Tegra timer source gets switched
off from the NS world leading to a DoS attack for the trusted world.

This timer is shared with the S-EL1 layer for now, but later patches
will mark it as exclusive to the EL3 exception mode.

Change-Id: I2c00f8cb4c48b25578971c626c314603906ad7cc
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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include: move MHZ_TICKS_PER_SEC to utils_def.h

This patch moves the MHZ_TICKS_PER_SEC macro to utils_def.h
for other platforms to use.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id:

include: move MHZ_TICKS_PER_SEC to utils_def.h

This patch moves the MHZ_TICKS_PER_SEC macro to utils_def.h
for other platforms to use.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I6c4dc733f548d73cfdb3515ec9ad89a9efaf4407

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Tegra194: memctrl: lock mc stream id security config

This patch locks most of the stream id security config registers as
per HW guidance.

This patch keeps the stream id configs unlocked for the fol

Tegra194: memctrl: lock mc stream id security config

This patch locks most of the stream id security config registers as
per HW guidance.

This patch keeps the stream id configs unlocked for the following
clients, to allow some platforms to still function, until they make
the transition to the latest guidance.

- ISPRA
- ISPFALR
- ISPFALW
- ISPWA
- ISPWA1
- ISPWB
- XUSB_DEVR
- XUSB_DEVW
- XUSB_HOSTR
- XUSB_HOSTW
- VIW
- VIFALR
- VIFALW

Change-Id: I66192b228a0a237035938f498babc0325764d5df
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

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Tegra210: resume PMC hardware block for all platforms

The PMC hardware block resume handler was called for Tegra210
platforms, only if the sc7entry-fw was present on the device.
This would cause pro

Tegra210: resume PMC hardware block for all platforms

The PMC hardware block resume handler was called for Tegra210
platforms, only if the sc7entry-fw was present on the device.
This would cause problems for devices that do not support this
firmware.

This patch fixes this logic and resumes the PMC block even if
the sc7entry-fw is not present on the device.

Change-Id: I6f0eb7878126f624ea98392f583ed45a231d27db
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>

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Tegra: macro for legacy WDT FIQ handling

This patch adds the macro to enable legacy FIQ handling to the common
Tegra makefile. The default value of this macro is '0'. Platforms that
need this suppor

Tegra: macro for legacy WDT FIQ handling

This patch adds the macro to enable legacy FIQ handling to the common
Tegra makefile. The default value of this macro is '0'. Platforms that
need this support should enable it from their makefiles.

This patch also helps fix violation of Rule 20.9.

Rule 20.9 "All identifiers used in the controlling expression of #if
of #elif preprocessing directives shall be #define'd before
evaluation"

Change-Id: I4f0c9917c044b5b1967fb5e79542cd3bf6e91f18
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: enable higher performance non-cacheable load forwarding

This patch enables higher performance non-cacheable load forwarding for
Tegra186 platforms.

Change-Id: Ifceb304bfbd805f415bb6205c96

Tegra186: enable higher performance non-cacheable load forwarding

This patch enables higher performance non-cacheable load forwarding for
Tegra186 platforms.

Change-Id: Ifceb304bfbd805f415bb6205c9679602ecb47b53
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra210: enable higher performance non-cacheable load forwarding

This patch enables higher performance non-cacheable load forwarding for
Tegra210 platforms.

Change-Id: I11d0ffc09aca97d37386f283f2f

Tegra210: enable higher performance non-cacheable load forwarding

This patch enables higher performance non-cacheable load forwarding for
Tegra210 platforms.

Change-Id: I11d0ffc09aca97d37386f283f2fbd2483d51fd28
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge "intel: Fix Coverity Scan Defects" into integration

intel: Fix Coverity Scan Defects

Fix mailbox driver incompatible cast bug and control flow issue that
was flagged by Coverity Scan.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.

intel: Fix Coverity Scan Defects

Fix mailbox driver incompatible cast bug and control flow issue that
was flagged by Coverity Scan.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I3f34e98d24e40139d31cf7d5b9b973cd2d981065

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Merge changes I72846d86,I70c3d873,If675796a,I0dbf8091,Ie4f3ac83, ... into integration

* changes:
rcar_gen3: plat: Minor coding style fix for rcar_version.h
rcar_gen3: plat: Update IPL and Secure

Merge changes I72846d86,I70c3d873,If675796a,I0dbf8091,Ie4f3ac83, ... into integration

* changes:
rcar_gen3: plat: Minor coding style fix for rcar_version.h
rcar_gen3: plat: Update IPL and Secure Monitor Rev.2.0.6
rcar_gen3: drivers: ddr: Update DDR setting for H3, M3, M3N
rcar_gen3: drivers: ddr: Update DDR setting for H3, M3, M3N
rcar_gen3: drivers: board: Add new board revision for M3ULCB
rcar_gen3: drivers: ddr: Update DDR setting for H3, M3, M3N
rcar_gen3: plat: Update IPL and Secure Monitor Rev.2.0.5
rcar_gen3: plat: Change fixed destination address of BL31 and BL32

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board/rddaniel: intialize tzc400 controllers

A TZC400 controller is placed inline on DRAM channels and regulates
the secure and non-secure accesses to both secure and non-secure
regions of the DRAM

board/rddaniel: intialize tzc400 controllers

A TZC400 controller is placed inline on DRAM channels and regulates
the secure and non-secure accesses to both secure and non-secure
regions of the DRAM memory. Configure each of the TZC controllers
accordingly.

Change-Id: I75f6d13591a7fe9e50ce15c793e35a8018041815
Signed-off-by: Suyash Pathak <suyash.pathak@arm.com>

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plat/arm/tzc: add support to configure multiple tzc400

For platforms that have two or more TZC400 controllers instantiated,
allow the TZC400 driver to be usable with all those instances.
This is ach

plat/arm/tzc: add support to configure multiple tzc400

For platforms that have two or more TZC400 controllers instantiated,
allow the TZC400 driver to be usable with all those instances.
This is achieved by allowing 'arm_tzc400_setup' function to accept
the base address of the TZC400 controller.

Change-Id: I4add470e6ddb58432cd066145e644112400ab924
Signed-off-by: Suyash Pathak <suyash.pathak@arm.com>

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plat/arm: allow boards to specify second DRAM Base address

The base address for second DRAM varies across different platforms.
So allow platforms to define second DRAM by moving Juno/SGM-775 specifi

plat/arm: allow boards to specify second DRAM Base address

The base address for second DRAM varies across different platforms.
So allow platforms to define second DRAM by moving Juno/SGM-775 specific
definition of second DRAM base address to Juno/SGM-775 board definition
respectively, SGI/RD specific definition of DRAM 2 base address to SGI
board definition.

Change-Id: I0ecd3a2bd600b6c7019c7f06f8c452952bd07cae
Signed-off-by: Suyash Pathak <suyash.pathak@arm.com>

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plat/arm: allow boards to define PLAT_ARM_TZC_FILTERS

A TZC400 can have upto 4 filters and the number of filters instantiated
within a TZC400 is platform dependent. So allow platforms to define the

plat/arm: allow boards to define PLAT_ARM_TZC_FILTERS

A TZC400 can have upto 4 filters and the number of filters instantiated
within a TZC400 is platform dependent. So allow platforms to define the
value of PLAT_ARM_TZC_FILTERS by moving the existing Juno specific
definition of PLAT_ARM_TZC_FILTERS to Juno board definitions.

Change-Id: I67a63d7336595bbfdce3163f9a9473e15e266f40
Signed-off-by: Suyash Pathak <suyash.pathak@arm.com>

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board/rdn1edge: use CREATE_SEQ helper macro to compare chip count

Use CREATE_SEQ helper macro to create sequence of valid chip counts
instead of manually creating the sequence. This allows a scalabl

board/rdn1edge: use CREATE_SEQ helper macro to compare chip count

Use CREATE_SEQ helper macro to create sequence of valid chip counts
instead of manually creating the sequence. This allows a scalable
approach to increase the valid chip count sequence in the future.

Change-Id: I5ca7a00460325c156b9e9e52b2bf656a2e43f82d
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>

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Merge changes from topic "corstone700" into integration

* changes:
corstone700: set UART clocks to 32MHz
corstone700: clean-up as per coding style guide
Corstone700: add support for mhuv2 in a

Merge changes from topic "corstone700" into integration

* changes:
corstone700: set UART clocks to 32MHz
corstone700: clean-up as per coding style guide
Corstone700: add support for mhuv2 in arm TF-A

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Add Matterhorn CPU lib

Also update copyright statements

Change-Id: Iba0305522ac0f2ddc4da99127fd773f340e67300
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

Add CPULib for Klein Core

Change-Id: I686fd623b8264c85434853a2a26ecd71e9eeac01
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

FVP: Fix BL31 load address and image size for RESET_TO_BL31=1

When TF-A is built with RESET_TO_BL31=1 option, BL31 is the
first image to be run and should have all the memory allocated
to it except

FVP: Fix BL31 load address and image size for RESET_TO_BL31=1

When TF-A is built with RESET_TO_BL31=1 option, BL31 is the
first image to be run and should have all the memory allocated
to it except for the memory reserved for Shared RAM at the start
of Trusted SRAM.
This patch fixes FVP BL31 load address and its image size for
RESET_TO_BL31=1 option. BL31 startup address should be set to
0x400_1000 and its maximum image size to the size of Trusted SRAM
minus the first 4KB of shared memory.
Loading BL31 at 0x0402_0000 as it is currently stated in
'\docs\plat\arm\fvp\index.rst' causes EL3 exception when the
image size gets increased (i.e. building with LOG_LEVEL=50)
but doesn't exceed 0x3B000 not causing build error.

Change-Id: Ie450baaf247f1577112f8d143b24e76c39d33e91
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

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corstone700: set UART clocks to 32MHz

Adding support for 32MHz UART clock and selecting it as the
default UART clock

Change-Id: I9541eaff70424e85a3b5ee4820ca0e7efb040d2c
Signed-off-by: Vishnu Banav

corstone700: set UART clocks to 32MHz

Adding support for 32MHz UART clock and selecting it as the
default UART clock

Change-Id: I9541eaff70424e85a3b5ee4820ca0e7efb040d2c
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>

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corstone700: clean-up as per coding style guide

Running checkpatch.pl on the codebase and making required changes

Change-Id: I7d3f8764cef632ab2a6d3c355c68f590440b85b8
Signed-off-by: Avinash Mehta <

corstone700: clean-up as per coding style guide

Running checkpatch.pl on the codebase and making required changes

Change-Id: I7d3f8764cef632ab2a6d3c355c68f590440b85b8
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>

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Corstone700: add support for mhuv2 in arm TF-A

Note: This patch implements in-band messaging protocol only.
ARM has launched a next version of MHU i.e. MHUv2 with its latest
subsystems. The main cha

Corstone700: add support for mhuv2 in arm TF-A

Note: This patch implements in-band messaging protocol only.
ARM has launched a next version of MHU i.e. MHUv2 with its latest
subsystems. The main change is that the MHUv2 is now a distributed IP
with different peripheral views (registers) for the sender and receiver.

Another main difference is that MHUv1 duplex channels are now split into
simplex/half duplex in MHUv2. MHUv2 has a configurable number of
communication channels. There is a capability register (MSG_NO_CAP) to
find out how many channels are available in a system.

The register offsets have also changed for STAT, SET & CLEAR registers
from 0x0, 0x8 & 0x10 in MHUv1 to 0x0, 0xC & 0x8 in MHUv2 respectively.

0x0 0x4 0x8 0xC 0x1F
------------------------....-----
| STAT | | | SET | | |
------------------------....-----
Transmit Channel

0x0 0x4 0x8 0xC 0x1F
------------------------....-----
| STAT | | CLR | | | |
------------------------....-----
Receive Channel

The MHU controller can request the receiver to wake-up and once the
request is removed, the receiver may go back to sleep, but the MHU
itself does not actively put a receiver to sleep.

So, in order to wake-up the receiver when the sender wants to send data,
the sender has to set ACCESS_REQUEST register first in order to wake-up
receiver, state of which can be detected using ACCESS_READY register.
ACCESS_REQUEST has an offset of 0xF88 & ACCESS_READY has an offset
of 0xF8C and are accessible only on any sender channel.

This patch adds necessary changes in a new file required to support the
latest MHUv2 controller. This patch also needs an update in DT binding
for ARM MHUv2 as we need a second register base (tx base) which would
be used as the send channel base.

Change-Id: I1455e08b3d88671a191c558790c503eabe07a8e6
Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>

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rockchip: fix definition of struct param_ddr_usage

In extreme cases, the number of secure regions is one more than
non-secure regions. So array "s_base" and "s_top"s size
in struct param_ddr_usage n

rockchip: fix definition of struct param_ddr_usage

In extreme cases, the number of secure regions is one more than
non-secure regions. So array "s_base" and "s_top"s size
in struct param_ddr_usage need to be adjust to "DDR_REGION_NR_MAX + 1".

Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: Ifc09da2c8f8afa1aebcc78f8fbc21ac95abdece2

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rcar_gen3: plat: Minor coding style fix for rcar_version.h

Use space after #define consistently, drop useless parenthesis,
no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmai

rcar_gen3: plat: Minor coding style fix for rcar_version.h

Use space after #define consistently, drop useless parenthesis,
no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I72846d8672cab09b128e3118f4b7042a5a9c0df5

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