Merge changes from topic "fpga_generic" into integration

* changes:
arm_fpga: Add platform documentation
arm_fpga: Add post-build linker script
arm_fpga: Add ROM trampoline
arm_fpga: Add dev

Merge changes from topic "fpga_generic" into integration

* changes:
arm_fpga: Add platform documentation
arm_fpga: Add post-build linker script
arm_fpga: Add ROM trampoline
arm_fpga: Add devicetree file
arm_fpga: Remove SPE PMU DT node if SPE is not available
arm_fpga: Adjust GICR size in DT to match number of cores
fdt: Add function to adjust GICv3 redistributor size
drivers: arm: gicv3: Allow detecting number of cores

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arm_fpga: Add post-build linker script

For the Arm Ltd. FPGAs to run, we need to load several payloads into the
FPGA's memory:
- Some trampoline code at address 0x0, to jump to BL31's entry point.
-

arm_fpga: Add post-build linker script

For the Arm Ltd. FPGAs to run, we need to load several payloads into the
FPGA's memory:
- Some trampoline code at address 0x0, to jump to BL31's entry point.
- The actual BL31 binary at the beginning of DRAM.
- The (generic) DTB image to describe the hardware.
- The actual non-secure payloads (kernel, ramdisks, ...)

The latter is application specific, but the first three blobs are rather
generic.
Since the uploader tool supports ELF binaries, it seems helpful to
combine these three images into one .axf file, as this also simplifies
the command line.

Add a post-build linker script, that combines those three bits into one
ELF file, together with their specific load addresses.
Include a call to "ld" with this linker script in the platform Makefile,
so it will be build automatically. The result will be called "bl31.axf".

Change-Id: I4a90da16fa1e0e83b51d19e5b1daf61f5a0bbfca
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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arm_fpga: Add ROM trampoline

The application cores of the FPGAs used in Arm Ltd. start execution at
address 0x0. This is the location of some (emulated) ROM area (which can
be written to by the uplo

arm_fpga: Add ROM trampoline

The application cores of the FPGAs used in Arm Ltd. start execution at
address 0x0. This is the location of some (emulated) ROM area (which can
be written to by the uploading tool).
Since the arm_fpga port is configured to run from DRAM, we load BL31 to
the beginning of DRAM (mapped at 2GB). This requires some small
trampoline code in the "ROM" to jump to the BL31 entry point.

To avoid some extra magic binary, add a tiny assembly file with that
trivial jump instruction to the tree, so this binary can be created
alongside BL31.

Change-Id: I9e4439fc0f093fa24dd49a8377c9edb030fbb477
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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arm_fpga: Add devicetree file

The FPGA images used in Arm Ltd. focus on CPU cores, so they share a
common platform, with a minimal set of peripherals (interconnect, GIC,
UART).
This allows to suppor

arm_fpga: Add devicetree file

The FPGA images used in Arm Ltd. focus on CPU cores, so they share a
common platform, with a minimal set of peripherals (interconnect, GIC,
UART).
This allows to support most platforms with a single devicetree file.
The topology and number of CPU cores differ, but those will added at
runtime, in BL31. Other adjustments (GICR size, SPE node, command line)
are also done at this point.

Add the common devicetree file to TF-A's build system, so it can be
build together with BL31. At runtime, the resulting .dtb file should be
uploaded to the address given with FPGA_PRELOADED_DTB_BASE at build time.

Change-Id: I3206d6131059502ec96896e95329865452c9d83e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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arm_fpga: Remove SPE PMU DT node if SPE is not available

The Statistical Profiling Extension (SPE) is an architectural feature we
can safely detect at runtime. However it still relies on one piece o

arm_fpga: Remove SPE PMU DT node if SPE is not available

The Statistical Profiling Extension (SPE) is an architectural feature we
can safely detect at runtime. However it still relies on one piece of
platform-specific information: the interrupt line it is connected
to. This requires SPE to be described in a devicetree node.

Since SPE support varies with the CPU cores found on an FPGA image, we
should detect the presence of SPE at runtime, and remove a potentially
existing SPE PMU node from the DT.

This allows to always have the SPE node in a generic devicetree file,
without risking exposing it on a CPU without this feature.

Change-Id: I73d83ea8509b03fe7bba20b9cce8d1335035fa31
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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arm_fpga: Adjust GICR size in DT to match number of cores

The size of a GICv3 redistributor region depends on the number of
cores in the system. For the ARM FPGA port, we detect the topology at
runt

arm_fpga: Adjust GICR size in DT to match number of cores

The size of a GICv3 redistributor region depends on the number of
cores in the system. For the ARM FPGA port, we detect the topology at
runtime, and adjust the CPU DT nodes accordingly.
Now the size of the GICR region must also be adjusted, or Linux will
fail to initialise the GICv3.

Use the newly introduced function to overwrite the GICR size entry in
the GICv3 reg property. We count the number of existing cores by
iterating over the GICR frames until we find the LAST bit set in TYPER.

Change-Id: Ib69565600859de9b1b15ceb8495172cd26d16fce
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes I1ecbe5a1,Ib5945c37,Ic6b79648 into integration

* changes:
plat/arm: Add platform support for Morello
fdts: add device tree sources for morello platform
lib/cpus: add support for

Merge changes I1ecbe5a1,Ib5945c37,Ic6b79648 into integration

* changes:
plat/arm: Add platform support for Morello
fdts: add device tree sources for morello platform
lib/cpus: add support for Morello Rainier CPUs

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Merge "arm_fpga: Add support for unknown MPIDs" into integration

plat/arm: Add platform support for Morello

This patch adds support for Morello platform.
It is an initial port which includes only BL31 support
as the System Control Processor (SCP) is expected to t

plat/arm: Add platform support for Morello

This patch adds support for Morello platform.
It is an initial port which includes only BL31 support
as the System Control Processor (SCP) is expected to take
the role of primary bootloader.

Change-Id: I1ecbe5a14a2d487b2ecea3c1ca227f08473ed2dd
Co-authored-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Signed-off-by: Anurag Koul <anurag.koul@arm.com>

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arm_fpga: Add support for unknown MPIDs

This patch allows the system to fallback to a default CPU library
in case the MPID does not match with any of the supported ones.

This feature can be enabled

arm_fpga: Add support for unknown MPIDs

This patch allows the system to fallback to a default CPU library
in case the MPID does not match with any of the supported ones.

This feature can be enabled by setting SUPPORT_UNKNOWN_MPID build
option to 1 (enabled by default only on arm_fpga platform).

This feature can be very dangerous on a production image and
therefore it MUST be disabled for Release images.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I0df7ef2b012d7d60a4fd5de44dea1fbbb46881ba

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Merge changes from topic "tc0_architecture_change" into integration

* changes:
plat: tc0: enable TZC
fdts: tc0: update MHUv2 interrupt number

mediatek: mt8192: add GIC600 support

1. Implement GIC600 driver support and init
2. Remove unused debug info

Signed-off-by: Greta Zhang <greta.zhang@mediatek.com>
Change-Id: I30c08c531e705debc02907

mediatek: mt8192: add GIC600 support

1. Implement GIC600 driver support and init
2. Remove unused debug info

Signed-off-by: Greta Zhang <greta.zhang@mediatek.com>
Change-Id: I30c08c531e705debc029071e4e970048e261c386

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Merge "plat/arm/css/sgi: Map flash used for mem_protect" into integration

Merge "plat/arm: Introduce and use libc_asm.mk makefile" into integration

plat/arm/css/sgi: Map flash used for mem_protect

The SGI platform defines the macro PLAT_ARM_MEM_PROT_ADDR which
indicates that the platform has mitigation for cold reboot attacks.

However, the fla

plat/arm/css/sgi: Map flash used for mem_protect

The SGI platform defines the macro PLAT_ARM_MEM_PROT_ADDR which
indicates that the platform has mitigation for cold reboot attacks.

However, the flash memory used for the mem_protect region was not
mapped. This results in a crash when an OS calls PSCI MEM_PROTECT.

To fix this map the flash region used for mem_protect.

Change-Id: Ia494f924ecfe2ce835c045689ba8f942bf0941f4
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>

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plat: tc0: enable TZC

Change-Id: Ic2bb8482f0b602f6b7850d4fa553448bc4931edc
Signed-off-by: Usama Arif <usama.arif@arm.com>

fdts: stm32mp1: realign device tree with kernel

There is one dtsi file per SoC version:
- STM32MP151: common part for all version, Single Cortex-A7
- STM32MP153: Dual Cortex-A7
- STM32MP157: + GPU a

fdts: stm32mp1: realign device tree with kernel

There is one dtsi file per SoC version:
- STM32MP151: common part for all version, Single Cortex-A7
- STM32MP153: Dual Cortex-A7
- STM32MP157: + GPU and DSI, but not needed for TF-A

The STM32MP15xC include a cryptography peripheral, add it in a dedicated
file.

There are 4 packages available, for which the IOs number change. Have one
file for each package. The 2 packages AB and AD are added.

STM32157A-DK1 and STM32MP157C-DK2 share most of their features, a common
dkx file is then created.

Some reordering is done in other files, and realign with kernel DT files.

The DDR files are generated with our internal tool, no changes in the
registers values.

Change-Id: I9f2ef00306310abe34b94c2f10fc7a77a10493d1
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge "SPMC: adjust the number of EC context to max number of PEs" into integration

stm32mp1: correct crash console GPIO alternate configuration

If GPIO port for UART TX is less than 8, the register GPIO_AFRL should
be used to set the alternate. GPIO_AFRH is used if GPIO port is gr

stm32mp1: correct crash console GPIO alternate configuration

If GPIO port for UART TX is less than 8, the register GPIO_AFRL should
be used to set the alternate. GPIO_AFRH is used if GPIO port is greater
or equal to 8. The macro GPIO_TX_ALT_SHIFT is removed and the GPIO port
number is tested against GPIO_ALT_LOWER_LIMIT (=8) in
plat_crash_console_init() function.

Change-Id: Ibb62223ed6bce589bbcab59a5e986b2677e6d118
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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stm32mp1: add plat_panic_handler function

The STM32MP1 implementation of this function will call
plat_report_exception(). It displays more information about the panic
if DEBUG is enabled.
The LR reg

stm32mp1: add plat_panic_handler function

The STM32MP1 implementation of this function will call
plat_report_exception(). It displays more information about the panic
if DEBUG is enabled.
The LR register is also filled with R6 content, which hold the faulty
address. This allows debugger to reconstruct the backtrace.

Change-Id: I6710e8e2ab6658b05c5bbad2f3c545f07f355afb
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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stm32mp1: update plat_report_exception

In case DEBUG is enabled, plat_report_exception will now display extra
information of the cause of the exception.

Change-Id: I72cc9d180959cbf31c13821dd051eaf4

stm32mp1: update plat_report_exception

In case DEBUG is enabled, plat_report_exception will now display extra
information of the cause of the exception.

Change-Id: I72cc9d180959cbf31c13821dd051eaf4462b733e
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge "build_macros.mk: include assert and define loop macros" into integration

Merge changes from topic "ehf_common" into integration

* changes:
plat: tegra: Use generic ehf defines
ehf: use common priority level enumuration

SPMC: adjust the number of EC context to max number of PEs

According to [1] and in context of FF-A v1.0 a secure partition must
have either one EC (migratable UP) or a number of ECs equal to the
num

SPMC: adjust the number of EC context to max number of PEs

According to [1] and in context of FF-A v1.0 a secure partition must
have either one EC (migratable UP) or a number of ECs equal to the
number of PEs (pinned MP). Adjust the SPMC manifest such that the
number of ECs is equal to the number of PEs.

[1] https://trustedfirmware-a.readthedocs.io/en/latest/components/
secure-partition-manager.html#platform-topology

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ie8c7d96ae7107cb27f5b97882d8f476c18e026d4

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plat/arm: fvp: Increase BL2 maximum size

Increased BL2 maximum size when CoT descriptors are placed
in device tree.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I6466d2841e

plat/arm: fvp: Increase BL2 maximum size

Increased BL2 maximum size when CoT descriptors are placed
in device tree.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I6466d2841e189e7f15eb4f1a8db070542893cb5b

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