stm32mp1: update rules for stm32image tool

In heavy parallel builds, it has sometimes been seen issues with the
tool not generated before it was needed. Change some rules order and
dependency to sol

stm32mp1: update rules for stm32image tool

In heavy parallel builds, it has sometimes been seen issues with the
tool not generated before it was needed. Change some rules order and
dependency to solve that.

Change-Id: I8f4b4f46a2ea0fe496bc66bca47c66d1c81d3c99
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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stm32mp1: add macros to define PLAT_PARTITION_MAX_ENTRIES

There were fixed values when computing PLAT_PARTITION_MAX_ENTRIES.
Use STM32_BL33_PARTS_NUM and STM32_RUNTIME_PARTS_NUM. The first one is
fo

stm32mp1: add macros to define PLAT_PARTITION_MAX_ENTRIES

There were fixed values when computing PLAT_PARTITION_MAX_ENTRIES.
Use STM32_BL33_PARTS_NUM and STM32_RUNTIME_PARTS_NUM. The first one is
for the number of copies of BL33. The second one depends on the use case
SP_min or OP-TEE. For OP-TEE, there are 3 partitions. For SP_min, as it
is in the same binary as BL2, it is set to 0. It will be set to 1 if
BL32 is in a separate binary.

Change-Id: Iba4d8ec5fbc713bebfbdcd9f9426c3fded20d3ad
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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stm32mp1: sort platform.mk

First put Makefile variables definition, then definitions for each feature,
then C flags, then source files, then compilation rules.

Change-Id: I238115ea2fe4ebafccd213597

stm32mp1: sort platform.mk

First put Makefile variables definition, then definitions for each feature,
then C flags, then source files, then compilation rules.

Change-Id: I238115ea2fe4ebafccd2135979814c27932c34e2
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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stm32mp1: use ASFLAGS for binary paths

To simplify the rule that creates the concatenated binary, use ASFLAGS
instead of adding all paths in the AS command line. This allows a better
management if a

stm32mp1: use ASFLAGS for binary paths

To simplify the rule that creates the concatenated binary, use ASFLAGS
instead of adding all paths in the AS command line. This allows a better
management if a binary is not present.

Change-Id: Ic8b4566e7dedc6f55be355a92e3b214cef138d9b
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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stm32mp1: use internal MAKE_LD macro to generate stm32 linker files

The previous proprietary version was not correctly handling dependencies.
Using MAKE_LD from make_helpers files now correctly hand

stm32mp1: use internal MAKE_LD macro to generate stm32 linker files

The previous proprietary version was not correctly handling dependencies.
Using MAKE_LD from make_helpers files now correctly handles that.
The generated linker script is the same as before.

Change-Id: Iccfd8dc3fffa7a33e73b184b72e0dfd5d26bc9c9
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge changes from topics "rename-herculesae-a78ae", "rename-zeus-v1" into integration

* changes:
Rename Neoverse Zeus to Neoverse V1
Rename Cortex Hercules AE to Cortex 78 AE

plat/arm: common: add guard for arm_get_rotpk_info_regs

Only define arm_get_rotpk_info_regs if ROTPK is in registers,
i.e. (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_REGS_ID). This will
allow platform buil

plat/arm: common: add guard for arm_get_rotpk_info_regs

Only define arm_get_rotpk_info_regs if ROTPK is in registers,
i.e. (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_REGS_ID). This will
allow platform build without definition of TZ_PUB_KEY_HASH_BASE
if dedicated registers for ROTPK are not available on the platform.

Change-Id: I74ee2d5007f5d876a031a1efca20ebee2dede0c7
Signed-off-by: Usama Arif <usama.arif@arm.com>

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Merge changes I959d1343,I6992df1a,I687e35cb,Ia5f2ee31,Ifd0bc6aa, ... into integration

* changes:
docs: marvell: update mv_ddr branch
plat: marvell: armada: a3k: rename the UART images archive

Merge changes I959d1343,I6992df1a,I687e35cb,Ia5f2ee31,Ifd0bc6aa, ... into integration

* changes:
docs: marvell: update mv_ddr branch
plat: marvell: armada: a3k: rename the UART images archive
plat: marvell: armada: a3k: allow image load to RAM address 0
marvell: comphy: cp110: add support for USB comphy polarity invert
marvell: comphy: cp110: add support for SATA comphy polarity invert
marvell: comphy: cp110: implement erratum IPCE_COMPHY-1353
drivers: marvell: mochi: Update AP incoming masters secure level
plat: marvell: armada: add ccu window for workaround errata-id 3033912
plat: marvell: ap806: implement workaround for errata-id FE-4265711

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Rename Neoverse Zeus to Neoverse V1

Change-Id: Ieb411e2f8092fa82062e619305b680673a8f184f
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

Rename Cortex Hercules AE to Cortex 78 AE

Change-Id: Ic0ca51a855660509264ff0d084c068e1421ad09a
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

plat: marvell: armada: a3k: rename the UART images archive

Add *.bin extension to UART recovery images archive name.
Such naming will cause the UART recovery images to be copied to the
Buildroot out

plat: marvell: armada: a3k: rename the UART images archive

Add *.bin extension to UART recovery images archive name.
Such naming will cause the UART recovery images to be copied to the
Buildroot output folder upon flash image build.

Change-Id: I6992df1ab2ded725bed58e5baf245ae92c4cb289
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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plat: marvell: armada: a3k: allow image load to RAM address 0

Marvell uses RAM address 0x0 for loading BL33 stage images.
When ATF is built with DEBUG=1, its IO subsystem fails on
assert checking th

plat: marvell: armada: a3k: allow image load to RAM address 0

Marvell uses RAM address 0x0 for loading BL33 stage images.
When ATF is built with DEBUG=1, its IO subsystem fails on
assert checking the destination RAM address != 0.
This patch adds PLAT_ALLOW_ZERO_ADDR_COPY to A3K platform
allowing to bypass the above check in debug mode.

Change-Id: I687e35cb2e9dc3166bdaa81b3904c20b784c5c6a
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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marvell: comphy: cp110: add support for USB comphy polarity invert

The polarity inversion for USB was not tested due to lack of hw design
which requires it. Currently all supported boards doesn't re

marvell: comphy: cp110: add support for USB comphy polarity invert

The polarity inversion for USB was not tested due to lack of hw design
which requires it. Currently all supported boards doesn't require USB
phy polarity inversion, therefore COMPHY_POLARITY_NO_INVERT is set for
all boards. Enable the option for the ones that need it.

Change-Id: Ia5f2ee313a93962e94963e2dd8a759ef6d9da369
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

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marvell: comphy: cp110: add support for SATA comphy polarity invert

The cp110 comphy has ability to invert RX and/or TX polarity. Polarity
depends on board design. Currently all supported boards doe

marvell: comphy: cp110: add support for SATA comphy polarity invert

The cp110 comphy has ability to invert RX and/or TX polarity. Polarity
depends on board design. Currently all supported boards doesn't require
SATA phy polarity invert, therefore COMPHY_POLARITY_NO_INVERT is set for
all boards.

Change-Id: Ifd0bc6aaf8a76a0928132b197422f3193cf020d5
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

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plat: marvell: ap806: implement workaround for errata-id FE-4265711

ERRATA ID: FE-4265711 - Incorrect CNTVAL reading

CNTVAL reflects the global system counter value in binary format.
Due to this er

plat: marvell: ap806: implement workaround for errata-id FE-4265711

ERRATA ID: FE-4265711 - Incorrect CNTVAL reading

CNTVAL reflects the global system counter value in binary format.
Due to this erratum, the CNTVAL value presented to the processor
may be incorrect for several clock cycles.

Workaround: Override the default value of AP Register Device General
control 20 [19:16] and AP Register Device General Control 21 [11:8]
to the value of 0x3.

Change-Id: I1705608d08acd9631ab98d6f7ceada34d6b8336f
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

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Merge "fdts: stm32mp1: realign device tree with kernel" into integration

morello: Add changes to fix build of Morello Platform

This patch makes changes required to get the morello
platform working with the tip of TF-A.

Change-Id: I095006615c9959bba49fcc75b52e1de7d748630

morello: Add changes to fix build of Morello Platform

This patch makes changes required to get the morello
platform working with the tip of TF-A.

Change-Id: I095006615c9959bba49fcc75b52e1de7d7486309
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

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Merge changes from topic "stm32_exceptions" into integration

* changes:
stm32mp1: correct crash console GPIO alternate configuration
stm32mp1: add plat_panic_handler function
stm32mp1: update

Merge changes from topic "stm32_exceptions" into integration

* changes:
stm32mp1: correct crash console GPIO alternate configuration
stm32mp1: add plat_panic_handler function
stm32mp1: update plat_report_exception
Align AARCH32 version of debug.S with AARCH64

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Merge changes from topic "fpga_generic" into integration

* changes:
arm_fpga: Add platform documentation
arm_fpga: Add post-build linker script
arm_fpga: Add ROM trampoline
arm_fpga: Add dev

Merge changes from topic "fpga_generic" into integration

* changes:
arm_fpga: Add platform documentation
arm_fpga: Add post-build linker script
arm_fpga: Add ROM trampoline
arm_fpga: Add devicetree file
arm_fpga: Remove SPE PMU DT node if SPE is not available
arm_fpga: Adjust GICR size in DT to match number of cores
fdt: Add function to adjust GICv3 redistributor size
drivers: arm: gicv3: Allow detecting number of cores

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arm_fpga: Add post-build linker script

For the Arm Ltd. FPGAs to run, we need to load several payloads into the
FPGA's memory:
- Some trampoline code at address 0x0, to jump to BL31's entry point.
-

arm_fpga: Add post-build linker script

For the Arm Ltd. FPGAs to run, we need to load several payloads into the
FPGA's memory:
- Some trampoline code at address 0x0, to jump to BL31's entry point.
- The actual BL31 binary at the beginning of DRAM.
- The (generic) DTB image to describe the hardware.
- The actual non-secure payloads (kernel, ramdisks, ...)

The latter is application specific, but the first three blobs are rather
generic.
Since the uploader tool supports ELF binaries, it seems helpful to
combine these three images into one .axf file, as this also simplifies
the command line.

Add a post-build linker script, that combines those three bits into one
ELF file, together with their specific load addresses.
Include a call to "ld" with this linker script in the platform Makefile,
so it will be build automatically. The result will be called "bl31.axf".

Change-Id: I4a90da16fa1e0e83b51d19e5b1daf61f5a0bbfca
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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arm_fpga: Add ROM trampoline

The application cores of the FPGAs used in Arm Ltd. start execution at
address 0x0. This is the location of some (emulated) ROM area (which can
be written to by the uplo

arm_fpga: Add ROM trampoline

The application cores of the FPGAs used in Arm Ltd. start execution at
address 0x0. This is the location of some (emulated) ROM area (which can
be written to by the uploading tool).
Since the arm_fpga port is configured to run from DRAM, we load BL31 to
the beginning of DRAM (mapped at 2GB). This requires some small
trampoline code in the "ROM" to jump to the BL31 entry point.

To avoid some extra magic binary, add a tiny assembly file with that
trivial jump instruction to the tree, so this binary can be created
alongside BL31.

Change-Id: I9e4439fc0f093fa24dd49a8377c9edb030fbb477
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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arm_fpga: Add devicetree file

The FPGA images used in Arm Ltd. focus on CPU cores, so they share a
common platform, with a minimal set of peripherals (interconnect, GIC,
UART).
This allows to suppor

arm_fpga: Add devicetree file

The FPGA images used in Arm Ltd. focus on CPU cores, so they share a
common platform, with a minimal set of peripherals (interconnect, GIC,
UART).
This allows to support most platforms with a single devicetree file.
The topology and number of CPU cores differ, but those will added at
runtime, in BL31. Other adjustments (GICR size, SPE node, command line)
are also done at this point.

Add the common devicetree file to TF-A's build system, so it can be
build together with BL31. At runtime, the resulting .dtb file should be
uploaded to the address given with FPGA_PRELOADED_DTB_BASE at build time.

Change-Id: I3206d6131059502ec96896e95329865452c9d83e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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arm_fpga: Remove SPE PMU DT node if SPE is not available

The Statistical Profiling Extension (SPE) is an architectural feature we
can safely detect at runtime. However it still relies on one piece o

arm_fpga: Remove SPE PMU DT node if SPE is not available

The Statistical Profiling Extension (SPE) is an architectural feature we
can safely detect at runtime. However it still relies on one piece of
platform-specific information: the interrupt line it is connected
to. This requires SPE to be described in a devicetree node.

Since SPE support varies with the CPU cores found on an FPGA image, we
should detect the presence of SPE at runtime, and remove a potentially
existing SPE PMU node from the DT.

This allows to always have the SPE node in a generic devicetree file,
without risking exposing it on a CPU without this feature.

Change-Id: I73d83ea8509b03fe7bba20b9cce8d1335035fa31
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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arm_fpga: Adjust GICR size in DT to match number of cores

The size of a GICv3 redistributor region depends on the number of
cores in the system. For the ARM FPGA port, we detect the topology at
runt

arm_fpga: Adjust GICR size in DT to match number of cores

The size of a GICv3 redistributor region depends on the number of
cores in the system. For the ARM FPGA port, we detect the topology at
runtime, and adjust the CPU DT nodes accordingly.
Now the size of the GICR region must also be adjusted, or Linux will
fail to initialise the GICv3.

Use the newly introduced function to overwrite the GICR size entry in
the GICv3 reg property. We count the number of existing cores by
iterating over the GICR frames until we find the LAST bit set in TYPER.

Change-Id: Ib69565600859de9b1b15ceb8495172cd26d16fce
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes I1ecbe5a1,Ib5945c37,Ic6b79648 into integration

* changes:
plat/arm: Add platform support for Morello
fdts: add device tree sources for morello platform
lib/cpus: add support for

Merge changes I1ecbe5a1,Ib5945c37,Ic6b79648 into integration

* changes:
plat/arm: Add platform support for Morello
fdts: add device tree sources for morello platform
lib/cpus: add support for Morello Rainier CPUs

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