allwinner: psci: Drop MPIDR check from .pwr_domain_on

This duplicated the logic in psci_validate_mpidr() which was already
called from psci_cpu_on().

Change-Id: I96ee92f1ce3e9cc2985b4e229ba86ebd27b

allwinner: psci: Drop MPIDR check from .pwr_domain_on

This duplicated the logic in psci_validate_mpidr() which was already
called from psci_cpu_on().

Change-Id: I96ee92f1ce3e9cc2985b4e229ba86ebd27b79915
Signed-off-by: Samuel Holland <samuel@sholland.org>

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allwinner: psci: Drop .get_node_hw_state callback

This optional PSCI function was only implemented when SCPI was
available. However, the underlying SCPI function is not able to fulfill
the necessary

allwinner: psci: Drop .get_node_hw_state callback

This optional PSCI function was only implemented when SCPI was
available. However, the underlying SCPI function is not able to fulfill
the necessary contract. First, the SCPI protocol has no way to represent
HW_STANDBY at the CPU power level. Second, the SCPI implementation
maintains its own logical view of power states, and its implementation
of SCPI_CMD_GET_CSS_POWER_STATE does not actually query the hardware.
Thus it cannot provide "the physical view of power state", as required
for this function by the PSCI specification.

Since the function is optional, drop it.

Change-Id: I5f3a0810ac19ddeb3c0c5d35aeb09f09a0b80c1d
Signed-off-by: Samuel Holland <samuel@sholland.org>

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stm32mp1: correct plat_crash_console_flush()

The base address of UART peripheral should be given in R0, not in R1.
Otherwise the console_stm32_core_flush issues an assert message.
This issue was hig

stm32mp1: correct plat_crash_console_flush()

The base address of UART peripheral should be given in R0, not in R1.
Otherwise the console_stm32_core_flush issues an assert message.
This issue was highlighted with recent changes in console flush functions.

Change-Id: Iead01986fdbbf30ad2fd9fa515a1d2b611b4e591
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge changes I44ef50da,I9802e9a3 into integration

* changes:
plat/arm/css/sgi: Fix assert expression issue
plat/arm/css/sgi: Fix bl32 receive event - 0xC4000061 issue

Merge "plat: xilinx: versal: Remove code duplication" into integration

plat/arm/css/sgi: Fix assert expression issue

Violation of MISRA-C Rule 14.4

Signed-off-by: Ming Huang <huangming@linux.alibaba.com>
Change-Id: I44ef50dadb54fb056a91f3de962b6e63ba6d7ac4

plat/arm/css/sgi: Fix bl32 receive event - 0xC4000061 issue

The issue is that, when interrupt is triggered and RAS handler
is entered, after interrupt handler finishes, TF-A will re-enter
bl32 and t

plat/arm/css/sgi: Fix bl32 receive event - 0xC4000061 issue

The issue is that, when interrupt is triggered and RAS handler
is entered, after interrupt handler finishes, TF-A will re-enter
bl32 and then crash.
sdei_dispatch_event() may return failing result in some cases,
for example kernel may not have registered a handler or RAS event
may happen early during boot. We restore the NS context when
sdei_dispatch_event() returns failing result.

error log :
Received delegated event
X0 : 0xC4000061
X1 : 0x0
X2 : 0x0
X3 : 0x0
Received event - 0xC4000061 on cpu 0
UnRecognized Event - 0xC4000061
Failed delegated event 0xC4000061, Status Invalid Parameter
Unhandled Exception in EL3.
x30 = 0x000000000401f700
x0 = 0xfffffffffffffffe
x1 = 0xfffffffffffffffe
x2 = 0x00000000600003c0

Signed-off-by: Ming Huang <huangming@linux.alibaba.com>
Change-Id: I9802e9a32eee0ac3b5a8bcc0362d0b0e3b71dc9f

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Merge changes Ic9bacaf3,I99a18dbb,I34803060,I3ed55aa4,Ic8eed072, ... into integration

* changes:
doc: renesas: Update RZ/G2 code owner list
plat: renesas: rzg: DT memory node enhancements
rene

Merge changes Ic9bacaf3,I99a18dbb,I34803060,I3ed55aa4,Ic8eed072, ... into integration

* changes:
doc: renesas: Update RZ/G2 code owner list
plat: renesas: rzg: DT memory node enhancements
renesas: rzg: emmc: Enable RZ/G2M support
plat: renesas: rzg: Add HopeRun HiHope RZ/G2M board support
drivers: renesas: rzg: Add HiHope RZ/G2M board support
tools: renesas: Add tool support for RZ/G2 platforms

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plat/arm: css: Turn ON/OFF redistributor in sync with GIC CPU interface ON/OFF

Turn ON/OFF GIC redistributor in sync with GIC CPU interface ON/OFF.

Issue :
The Linux prompt hangs when all the cores

plat/arm: css: Turn ON/OFF redistributor in sync with GIC CPU interface ON/OFF

Turn ON/OFF GIC redistributor in sync with GIC CPU interface ON/OFF.

Issue :
The Linux prompt hangs when all the cores in a cluster are turned OFF
and we try to turn ON a core in that cluster. Previously when TF-A turns
ON a core, TF-A first turns ON the redistributor followed by the core.
This did not match the flow when turning OFF a core, as TF-A did not
turn OFF redistributor when the corresponding core[s] are disabled.
This hang is resolved by disabling redistributor as cores are disabled,
keeping them in sync.

Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com>
Change-Id: Ifd04fdcfd47b45e00f874f15b098471883d023f0

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plat: xilinx: versal: Remove code duplication

Some switch cases uses same operation. So, club switch cases
which uses same operation and remove duplicate code.

Signed-off-by: Rajan Vaja <rajan.vaja

plat: xilinx: versal: Remove code duplication

Some switch cases uses same operation. So, club switch cases
which uses same operation and remove duplicate code.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I260b474c0ff3f2ca102c32d4af2e4abba2b8f57c

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drivers: move scmi-msg out of st

Make the scmi-msg driver reused by others.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I5bc35fd4dab70f45c09b8aab65af4209cf23b124

qemu/qemu_sbsa: add support for sbsa-ref Embedded Controller

This allows PSCI in TF-A to signal platform power states to QEMU
via a controller in secure space.

This required a sbsa-ref specific ver

qemu/qemu_sbsa: add support for sbsa-ref Embedded Controller

This allows PSCI in TF-A to signal platform power states to QEMU
via a controller in secure space.

This required a sbsa-ref specific version of PSCI functions for the
platform. Also adjusted the MMU range to also include the new EC.

Add a new MMU region for the embedded controller and increase the
size of xlat tables by one for the new region.

Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Change-Id: Iece8a88947f11e82ab8988e460a8a66ad175a5ee

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qemu/qemu_sbsa: topology is different from qemu so add handling

sbsa-ref in QEMU creates clusers of 8 cores, it may create up to 512
cores in upto 64 clusters. Implement a qemu_sbsa specific topolog

qemu/qemu_sbsa: topology is different from qemu so add handling

sbsa-ref in QEMU creates clusers of 8 cores, it may create up to 512
cores in upto 64 clusters. Implement a qemu_sbsa specific topology file
and increase the BL31_SIZE to accommodate the bigger table sizes. Change
platform_def.h for new topology. Correct PLATFORM_CPU_PER_CLUSTER_SHIFT so
plat_helpers.S calculates correct result.

Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Change-Id: Idc5d70394c0956b759ad2c86f9fda8f293f2cfa7

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qemu/common : change DEVICE2 definition for MMU

DEVICE2 is not currently used on qemu platform but is needed for
a future patch for qemu_sbsa platform. Change its definition to
RW and add it to all

qemu/common : change DEVICE2 definition for MMU

DEVICE2 is not currently used on qemu platform but is needed for
a future patch for qemu_sbsa platform. Change its definition to
RW and add it to all levels of arm-tf similar to DEVICE1 definition.

Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Change-Id: I03495471bfd423b61ad44ec4953fb25f76aa54bf

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qemu/aarch64/plat_helpers.S : calculate the position shift

Rather than re-create this file in multiple qemu variants instead
caclulate the shift needed to convert MPIDR to position.

Add a new PLATF

qemu/aarch64/plat_helpers.S : calculate the position shift

Rather than re-create this file in multiple qemu variants instead
caclulate the shift needed to convert MPIDR to position.

Add a new PLATFORM_CPU_PER_CLUSTER_SHIFT define in platform_def.h
for both qemu and qemu_sbsa to enable this calculation.

Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Change-Id: I0e3a86354aa716d95150a3a34b15287cd70c8fd2

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plat/qemu: Use RNDR in stack protector

When getting a stack protector canary value, check
if cpu supports FEAT_RNG and use that. Fallback to
old method of using a (hardcoded value ^ timer).

Signed-

plat/qemu: Use RNDR in stack protector

When getting a stack protector canary value, check
if cpu supports FEAT_RNG and use that. Fallback to
old method of using a (hardcoded value ^ timer).

Signed-off-by: Tomas Pilar <tomas@nuviainc.com>
Change-Id: I8181acf8e31661d4cc82bc3a4078f8751909e725

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plat: renesas: rzg: DT memory node enhancements

Add DT node support for channel 0 where physical memory is split
between 32bit space and 64bit space.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas

plat: renesas: rzg: DT memory node enhancements

Add DT node support for channel 0 where physical memory is split
between 32bit space and 64bit space.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I99a18dbb14cdb54100a836c16445242e430794e3

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plat: renesas: rzg: Add HopeRun HiHope RZ/G2M board support

The HiHope RZ/G2M board from HopeRun consists of main board
(HopeRun HiHope RZ/G2M main board) and sub board(HopeRun
HiHope RZ/G2M sub boa

plat: renesas: rzg: Add HopeRun HiHope RZ/G2M board support

The HiHope RZ/G2M board from HopeRun consists of main board
(HopeRun HiHope RZ/G2M main board) and sub board(HopeRun
HiHope RZ/G2M sub board). The HiHope RZ/G2M sub board sits
below the HiHope RZ/G2M main board.

This patch adds the required board support to boot HopeRun HiHope
RZ/G2M board.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I3ed55aa4a2cc5c9d9cd6440e087bcd93186520c7

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plat: renesas: common: Include ulcb_cpld.h conditionally

Include header ulcb_cpld.h in plat_pm.c only if RCAR_GEN3_ULCB
is enabled.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by:

plat: renesas: common: Include ulcb_cpld.h conditionally

Include header ulcb_cpld.h in plat_pm.c only if RCAR_GEN3_ULCB
is enabled.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Ie89223097c608265c50e32778e8df28feed82480

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plat: renesas: Move to common

Move rcar plat code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.c

plat: renesas: Move to common

Move rcar plat code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I1001bea1a8a9232a03ddbf6931ca3c764ba1e181

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plat: renesas: aarch64: Move to common

Move plat aarch64 code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das.jz@

plat: renesas: aarch64: Move to common

Move plat aarch64 code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I66265e5e68bfcf5c3534965fb3549a145c782b47

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drivers: renesas: Move ddr/qos/qos header files

Move DDR/QoS/PFC header files, so that the same code
can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das.jz@bp.r

drivers: renesas: Move ddr/qos/qos header files

Move DDR/QoS/PFC header files, so that the same code
can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I2cc0ceda8d05b6b8d95a69afdc233dc0d098e850

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drivers: renesas: rpc: Move to common

Move rpc driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das.jz@bp.

drivers: renesas: rpc: Move to common

Move rpc driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I04805d720d95b8edcc14e652f897fadc7f432197

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drivers: renesas: avs: Move to common

Move avs driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das.jz@bp.

drivers: renesas: avs: Move to common

Move avs driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I85d9fa8b6abf158ce2521f1696478f7c5339fc42

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drivers: renesas: auth: Move to common

Move authentication driver code to common directory, so that the
same code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <bij

drivers: renesas: auth: Move to common

Move authentication driver code to common directory, so that the
same code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I02592dfc714998bf89b9feaa78f685ae36be6f59

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