| 332649da | 15-Mar-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "matterhorn_elp" into integration
* changes:
plat: tc0: add matterhorn_elp_arm library to tc0
cpus: add Matterhorn ELP ARM cpu library |
| e96fc8e7 | 11-Feb-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
SPM: declare third cactus instance as UP SP
The FF-A v1.0 spec allows two configurations for the number of EC/vCPU
instantiated in a Secure Partition:
-A MultiProcessor (MP) SP instantiates as many
SPM: declare third cactus instance as UP SP
The FF-A v1.0 spec allows two configurations for the number of EC/vCPU
instantiated in a Secure Partition:
-A MultiProcessor (MP) SP instantiates as many ECs as the number of PEs.
An EC is pinned to a corresponding physical CPU.
-An UniProcessor (UP) SP instantiates a single EC. The EC is migrated to
the physical CPU from which the FF-A call is originating.
This change permits exercising the latter case within the TF-A-tests
framework.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I7fae0e7b873f349b34e57de5cea496210123aea0
show more ...
|
| 5491208a | 12-Mar-2021 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "linux_as_bl33" into integration
* changes:
plat/arm: Remove ARM_LINUX_KERNEL_AS_BL33 relying on RESET_TO_BL31
plat/arm: Always allow ARM_LINUX_KERNEL_AS_BL33 |
| 72bdcb9a | 29-Jan-2021 |
Usama Arif <usama.arif@arm.com> |
plat: tc0: add matterhorn_elp_arm library to tc0
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: Ie199c60553477c43d1665548ae78cdfd1aa7ffcf |
| a8fb76e5 | 10-Mar-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes I9c9ed516,I2788eaf6 into integration
* changes:
qemu/qemu_sbsa: fix memory type of secure NOR flash
qemu/qemu_sbsa: spm_mm supports 512 cores |
| ce19ac90 | 10-Mar-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "plat: xilinx: zynqmp: Add missing ids for 43/46/47dr devices" into integration |
| 682fe370 | 24-Sep-2020 |
Bharat Gooty <bharat.gooty@broadcom.com> |
driver: brcm: add USB driver
Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com>
Change-Id: I456aa7a641fffa8ea4e833615af3effec42a31b2 |
| c414019b | 08-Feb-2021 |
Heiko Stuebner <heiko.stuebner@theobroma-systems.com> |
plat/rockchip: Use common gicv2.mk
Compiling BL31 for the Rockchip platform now produces a message about
the deprecation of gic_common.c.
Follow the advice and use include gicv2.mk instead.
Signed-
plat/rockchip: Use common gicv2.mk
Compiling BL31 for the Rockchip platform now produces a message about
the deprecation of gic_common.c.
Follow the advice and use include gicv2.mk instead.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: I396b977d57975dba27cfed801ad5264bbbde2b5e
show more ...
|
| 6d98e750 | 08-Mar-2021 |
Roger Lu <roger.lu@mediatek.com> |
mediatek: mt8192: fix MISSING_BREAK
The case for value "VCOREFS_SMC_CMD_INIT" is not
terminated by a "break" statement.
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
Change-Id: I56cc7c1648e101c0d
mediatek: mt8192: fix MISSING_BREAK
The case for value "VCOREFS_SMC_CMD_INIT" is not
terminated by a "break" statement.
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
Change-Id: I56cc7c1648e101c0da6e77e592e6edbd5d37724e
show more ...
|
| a564bdc5 | 06-Jan-2021 |
Xi Chen <xixi.chen@mediatek.com> |
mediatek: mt8192: Add MPU Support for SCP/PCIe
1 Only enable domain D0 and D1:PCIe access 0xC0000000~0xC4000000;
2 Only enable domain D0 and D3(SCP) access 0x50000000~0x51400000;
Signed-off-by: Xi
mediatek: mt8192: Add MPU Support for SCP/PCIe
1 Only enable domain D0 and D1:PCIe access 0xC0000000~0xC4000000;
2 Only enable domain D0 and D3(SCP) access 0x50000000~0x51400000;
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: Ic4f9e6d85bfd1cebdb24ffc1d14309c89c103b2a
show more ...
|
| f3febcca | 14-Dec-2020 |
Roger Lu <roger.lu@mediatek.com> |
mediatek: mt8192: Add Vcore DVFS driver
Change-Id: I4bd4612a7c7727a5be70957ae940e5f51c7ca5e6
Signed-off-by: Roger Lu <roger.lu@mediatek.com> |
| ebb44440 | 03-Jan-2021 |
Roger Lu <roger.lu@mediatek.com> |
mediatek: mt8192: Add SPM suspend driver
Supports dram/mainpll/26m off when system suspend
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
Change-Id: Id13a06d4132f00fb60066de75920ecac18306e32 |
| df60025f | 03-Jan-2021 |
Roger Lu <roger.lu@mediatek.com> |
mediatek: mt8192: supports mcusys off when system suspend
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
Change-Id: I0ea7f61085ea9ba26c580107ef0cb9940a25f5e2 |
| cab49199 | 14-Dec-2020 |
Roger Lu <roger.lu@mediatek.com> |
mediatek: mt8192: Add lpm driver
Low Power Management (LPM) helps find a suitable configuration
for letting system entering idle or suspend with the most
resources off.
Change-Id: Ie6a7063b666cf338
mediatek: mt8192: Add lpm driver
Low Power Management (LPM) helps find a suitable configuration
for letting system entering idle or suspend with the most
resources off.
Change-Id: Ie6a7063b666cf338cff5bc972c9025b26de482eb
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
show more ...
|
| 1b7e5ca9 | 03-Mar-2021 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
plat: xilinx: zynqmp: Add missing ids for 43/46/47dr devices
Add support for ZU43DR, ZU46DR and ZU47DR to the list of zynqmp
devices. The ZU43DR, ZU46DR and ZU47DR RFSoC silicon id values are
0x7d,
plat: xilinx: zynqmp: Add missing ids for 43/46/47dr devices
Add support for ZU43DR, ZU46DR and ZU47DR to the list of zynqmp
devices. The ZU43DR, ZU46DR and ZU47DR RFSoC silicon id values are
0x7d, 0x78 and 0x7f.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@xilinx.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I566f707116d83475de7c87a6004ca96bf7bccebe
show more ...
|
| 8ef06b6c | 02-Mar-2021 |
bipin.ravi <bipin.ravi@arm.com> |
Merge "Add Makalu CPU lib" into integration |
| 4d9b9b23 | 25-Feb-2021 |
Tejas Patel <tejas.patel@xilinx.com> |
plat: xilinx: Add timeout while waiting for IPI Ack
Return timeout error if, IPI is not acked in specified timeout.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Change-Id: I27be3d4d4eb5bc57f
plat: xilinx: Add timeout while waiting for IPI Ack
Return timeout error if, IPI is not acked in specified timeout.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Change-Id: I27be3d4d4eb5bc57f6a84c839e2586278c0aec19
show more ...
|
| aaabf978 | 15-Oct-2020 |
johpow01 <john.powell@arm.com> |
Add Makalu CPU lib
Add basic support for Makalu CPU.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I4e85d425eedea499adf585eb8ab548931185043d |
| 174551d5 | 01-Mar-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "trng-svc" into integration
* changes:
plat/arm: juno: Use TRNG entropy source for SMCCC TRNG interface
plat/arm: juno: Condition Juno entropy source with CRC instructio
Merge changes from topic "trng-svc" into integration
* changes:
plat/arm: juno: Use TRNG entropy source for SMCCC TRNG interface
plat/arm: juno: Condition Juno entropy source with CRC instructions
show more ...
|
| 206fa996 | 01-Mar-2021 |
Masahisa Kojima <masahisa.kojima@linaro.org> |
qemu/qemu_sbsa: fix memory type of secure NOR flash
This commit fixes the wrong memory type, secure NOR flash
shall be mapped as MT_DEVICE.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.or
qemu/qemu_sbsa: fix memory type of secure NOR flash
This commit fixes the wrong memory type, secure NOR flash
shall be mapped as MT_DEVICE.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I9c9ed51675d84ded675bb56b2e4ec7a08184c602
show more ...
|
| cf952b0f | 02-Feb-2021 |
Masahisa Kojima <masahisa.kojima@linaro.org> |
qemu/qemu_sbsa: spm_mm supports 512 cores
sbsa-ref in QEMU may create up to 512 cores.
This commit prepares the MP information to support 512 cores.
The number of xlat tables for spm_mm is also incr
qemu/qemu_sbsa: spm_mm supports 512 cores
sbsa-ref in QEMU may create up to 512 cores.
This commit prepares the MP information to support 512 cores.
The number of xlat tables for spm_mm is also increased.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I2788eaf6d14e188e9b5d1102d359b2899e02df7c
show more ...
|
| 0aa70f4c | 25-Feb-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "plat/qemu: trigger reboot with secure pl061" into integration |
| 8909fa9b | 25-Feb-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I23f600b5,Icf9ffdf2,Iee7a51d1,I99afc312,I4bf8e8c0, ... into integration
* changes:
plat/marvell/armada: cleanup MSS SRAM if used for copy
plat/marvell: cn913x: allow CP1/CP2 mappin
Merge changes I23f600b5,Icf9ffdf2,Iee7a51d1,I99afc312,I4bf8e8c0, ... into integration
* changes:
plat/marvell/armada: cleanup MSS SRAM if used for copy
plat/marvell: cn913x: allow CP1/CP2 mapping at BLE stage
plat/marvell/armada/common/mss: use MSS SRAM in secure mode
include/drivers/marvell/mochi: add detection of secure mode
plat/marvell: fix SPD handling in dram port
marvell: drivers: move XOR0/1 DIOB from WIN 0 to 1
drivers/marvell/mochi: add support for cn913x in PCIe EP mode
drivers/marvell/mochi: add missing stream IDs configurations
plat/marvell/armada/a8k: support HW RNG by SMC
drivers/rambus: add TRNG-IP-76 driver
show more ...
|
| 5a9f5890 | 17-Jun-2020 |
Konstantin Porotchkin <kostap@marvell.com> |
plat/marvell/armada: cleanup MSS SRAM if used for copy
This patch cleans up the MSS SRAM if it was used for MSS image
copy (secure boot mode).
Change-Id: I23f600b512050f75e63d59541b9c21cef21ed313
S
plat/marvell/armada: cleanup MSS SRAM if used for copy
This patch cleans up the MSS SRAM if it was used for MSS image
copy (secure boot mode).
Change-Id: I23f600b512050f75e63d59541b9c21cef21ed313
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/30099
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
show more ...
|
| 109873cf | 29-Sep-2020 |
Konstantin Porotchkin <kostap@marvell.com> |
plat/marvell: cn913x: allow CP1/CP2 mapping at BLE stage
Map IO WIN to CP1 and CP2 at all stages including the BLE.
Do not map CP1/CP2 if CP_NUM is lower than 2 and 3 accordingly.
This patch allows
plat/marvell: cn913x: allow CP1/CP2 mapping at BLE stage
Map IO WIN to CP1 and CP2 at all stages including the BLE.
Do not map CP1/CP2 if CP_NUM is lower than 2 and 3 accordingly.
This patch allows access to CP1/CP2 internal registers at
BLE stage if CP1/CP2 are connected.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: Icf9ffdf2e9e3cdc2a153429ffd914cc0005f9eca
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/36939
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Yi Guo <yi.guo@cavium.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
show more ...
|