nxp: warm reset support to retain ddr content

NXP: Added warm reset handler to handle SMC PSCI_SYSTEM_RESET2
raised from kernel (> 5.4).

As part of first cold boot, DDR training data is stored in N

nxp: warm reset support to retain ddr content

NXP: Added warm reset handler to handle SMC PSCI_SYSTEM_RESET2
raised from kernel (> 5.4).

As part of first cold boot, DDR training data is stored in NV storage.

As part of this SMC handling, following things are done:
- DDR is put in self-refresh mode to retain the content of DDR.
- Reset cause is saved.
- Reset is triggered.

On next boot to last warm-reset, DDR training is restored from
the NV storage.

Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I8e4fb0824887af49e959c93825e2ab0ba887fc9d

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nxp: nv storage api on platforms

NV storage API(s) for NXP platforms, supported on:
- flexspi-nor
- SecMon - General Purpose Registers at Low-Power section,
retains their content if backe

nxp: nv storage api on platforms

NV storage API(s) for NXP platforms, supported on:
- flexspi-nor
- SecMon - General Purpose Registers at Low-Power section,
retains their content if backed by coined battery.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Id65dee4f28e7d6d2024407030039de33ebe0fa05

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nxp: supports two mode of trusted board boot

NXP SoC supports two TBB mode:
- MBED_TLS based
-- ROTK key hash is placed as part of the BL2 binary at section:
--- .rodata.nxp_rotpk_hash
-- S

nxp: supports two mode of trusted board boot

NXP SoC supports two TBB mode:
- MBED_TLS based
-- ROTK key hash is placed as part of the BL2 binary at section:
--- .rodata.nxp_rotpk_hash
-- Supporting non-volatile counter via SFP.
-- platform function used by TFA common authentication code.

- NXP CSF based
-- ROTK key deployment vary from MBEDTLS

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ib0f0bf024fd93de906c5d4f609383ae9e02b2fbc

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nxp: fip-handler for additional fip_fuse.bin

All of the NXP SoC, needs fip_fuse image to be
loaded additionally as part of preparation for Trusted board boot
- fip_fuse.bin contains an image for aut

nxp: fip-handler for additional fip_fuse.bin

All of the NXP SoC, needs fip_fuse image to be
loaded additionally as part of preparation for Trusted board boot
- fip_fuse.bin contains an image for auto fuse provisioning.
- Auto fuse provisioning is based on the input file with values for:
-- SRK Hash
-- OTPMK
-- misc. refer board manual for more details.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I26d4024fefe352d967ca120191f784f1f47aa9d1

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nxp: fip-handler for additional ddr-fip.bin

Few of the NXP SoC like LX2160A, needs ddr-phy images to be
loaded additionally before DDR initialization
- fip_ddr.bin is created containing upto 6 ddr i

nxp: fip-handler for additional ddr-fip.bin

Few of the NXP SoC like LX2160A, needs ddr-phy images to be
loaded additionally before DDR initialization
- fip_ddr.bin is created containing upto 6 ddr images.
- With TRUSTED_BOARD_BOOT = 1, fip_ddr.bin is authenticated
first before loading and starting DDR initialization.
- To successfully compile this image, platform-defined header files
needs to be defined:
-- include/common/tbbr/tbbr_img_def.h uses:
--- plat_tbbr_img_def.h: platform specific new FIP image macros.

-- include/tools/share/firmware_image_package.h uses:
--- plat_def_fip_uuid.h: platform specific new UUID macros.
---- Added UUID for DDR images to create FIP-DDR.
---- Added UUID for FUSE provisioning images to create FIP-fuse.

-- include/tools/share/tbbr_oid.h uses:
--- platform_oid.h: platform specific new OID macros.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Icbcf1673a8c398aae98680b5016f4276b4864b91

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nxp: image loader for loading fip image

function load_img(), is dependent on:
- Recursively calling load_image() defined in common/bl_common.c
- for each image in the fip.

Signed-off-by: Pankaj Gup

nxp: image loader for loading fip image

function load_img(), is dependent on:
- Recursively calling load_image() defined in common/bl_common.c
- for each image in the fip.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I57ca4b666cd1b0b992b7c0fc2a4260b558c0e2a9

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nxp: svp & sip smc handling

SMC call handling at EL3 due SIP and SVC calls.

Signed-off-by: rocket <rod.dorris@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: If86ee43477fc3b6

nxp: svp & sip smc handling

SMC call handling at EL3 due SIP and SVC calls.

Signed-off-by: rocket <rod.dorris@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: If86ee43477fc3b6116623928a3299d4e9015df8c

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nxp: psci platform functions used by lib/psci

Signed-off-by: rocket <rod.dorris@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I9853263ed38fb2a9f04b9dc7d768942e32074719

nxp: helper function used by plat & common code

Signed-off-by: rocket <rod.dorris@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Idafd8b0d94edf3515e8317431274d77289b7a1d0

nxp: add data handler used by bl31

bl31-data file written in assembly helps to manage data at bl31.

Signed-off-by: rocket <rod.dorris@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Cha

nxp: add data handler used by bl31

bl31-data file written in assembly helps to manage data at bl31.

Signed-off-by: rocket <rod.dorris@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ic3ace03364648cc1174bb05b5b334b9ccdaaa4ed

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allwinner: Use CPUIDLE hardware when available

This works even on SoCs that do not have an ARISC, and it avoids
clobbering whatever ARISC firmware might be running.

Change-Id: I9f2fed597189bb387de7

allwinner: Use CPUIDLE hardware when available

This works even on SoCs that do not have an ARISC, and it avoids
clobbering whatever ARISC firmware might be running.

Change-Id: I9f2fed597189bb387de79e8e76a7da3375e1ee91
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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plat: imx8mm: Add in BL2 with FIP

Adds bl2 with FIP to the build required for mbed Linux booting where
we do:

BootROM -> SPL -> BL2 -> OPTEE -> u-boot

If NEED_BL2 is specified then BL2 will be bui

plat: imx8mm: Add in BL2 with FIP

Adds bl2 with FIP to the build required for mbed Linux booting where
we do:

BootROM -> SPL -> BL2 -> OPTEE -> u-boot

If NEED_BL2 is specified then BL2 will be built and BL31 will have
its address range modified upwards to accommodate. BL31 must be
loaded from a FIP in this case.

If NEED_BL2 is not specified then the current BL31 boot flow is
unaffected and u-boot SPL will load and execute BL31 directly.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I655343b3b689b1fc57cfbedda4d3dc2fbd549a96

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plat: imx8mm: Add image load logic for TBBR FIP booting

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I0557ce6d0

plat: imx8mm: Add image load logic for TBBR FIP booting

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I0557ce6d0aa5ab321cac1ee25280b96762024396

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plat: imx8mm: Enable Trusted Boot

This patch enables Trusted Boot on the i.MX8MM with BL2 doing image
verification from a FIP prior to hand-over to BL31.

Signed-off-by: Bryan O'Donoghue <bryan.odon

plat: imx8mm: Enable Trusted Boot

This patch enables Trusted Boot on the i.MX8MM with BL2 doing image
verification from a FIP prior to hand-over to BL31.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I3c22783a5c49544d0bace8ef3724784b9b7cc64a

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plat: imx8mm: Add initial defintions to facilitate FIP layout

Adds a number of definitions consistent with the established WaRP7
equivalents specifying number of io_handles and block devices.

Signe

plat: imx8mm: Add initial defintions to facilitate FIP layout

Adds a number of definitions consistent with the established WaRP7
equivalents specifying number of io_handles and block devices.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: If1d7ef1ad3ac3dfc860f949392c7534ce8d206e3

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plat: imx8mm: Add image io-storage logic for TBBR FIP booting

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I983

plat: imx8mm: Add image io-storage logic for TBBR FIP booting

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I9833a54d0938d70886ac88b1922b17edf1dee8e0

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plat: imx8mm: Add imx8mm_private.h to the build

Allows for exporting of FIP related methods cleanly in a private header.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by:

plat: imx8mm: Add imx8mm_private.h to the build

Allows for exporting of FIP related methods cleanly in a private header.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I8523f1370312ed22ff7ca710cd916be52f725e3c

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stm32mp1: add TZC400 interrupt management

TZC400 is configured to raise an interrupt in case of faulty access.
Call the new added tzc400_it_handler, in case this interrupt occurs.

Change-Id: Iaf4fa

stm32mp1: add TZC400 interrupt management

TZC400 is configured to raise an interrupt in case of faulty access.
Call the new added tzc400_it_handler, in case this interrupt occurs.

Change-Id: Iaf4fa408a8eff99498042e11e2d6177bad39868c
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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stm32mp1: use TZC400 macro to describe filters

On STM32MP15, only filters 0 and 1 are used.
Use TZC_400_REGION_ATTR_FILTER_BIT() macro for those 2 filters 0 and 1
instead of U(3).

Change-Id: Ibc618

stm32mp1: use TZC400 macro to describe filters

On STM32MP15, only filters 0 and 1 are used.
Use TZC_400_REGION_ATTR_FILTER_BIT() macro for those 2 filters 0 and 1
instead of U(3).

Change-Id: Ibc61823842ade680f59d5b66b8db59b6a30080e4
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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rpi4: Switch to gicv2.mk and GICV2_SOURCES

Addresses the deprecation warning produced by
drivers/arm/gic/common/gic_common.c.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: I1a3ff483

rpi4: Switch to gicv2.mk and GICV2_SOURCES

Addresses the deprecation warning produced by
drivers/arm/gic/common/gic_common.c.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: I1a3ff4835d0f94c74b405db10622e99875ded82b

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plat: xilinx: versal: Mark IPI calls secure/non-secure

BIT24 of IPI command header is used to determine if caller is
secure or non-secure.

Mark BIT24 of IPI command header as non-secure if SMC call

plat: xilinx: versal: Mark IPI calls secure/non-secure

BIT24 of IPI command header is used to determine if caller is
secure or non-secure.

Mark BIT24 of IPI command header as non-secure if SMC caller
is non-secure.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: Iec25af8f4b202093f58e858ee47cd9cd46890267

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Merge "plat: xilinx: versal: Remove cortex-a53 compilation" into integration

Merge "plat: xilinx: Add timeout while waiting for IPI Ack" into integration

Merge changes from topic "od/ffa_spmc_pwr" into integration

* changes:
SPM: declare third cactus instance as UP SP
SPMD: lock the g_spmd_pm structure
FF-A: implement FFA_SECONDARY_EP_REGISTER

plat: xilinx: versal: Remove cortex-a53 compilation

Versal is a72 based that's why there is no reason to build low level
assemble code for a53.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

plat: xilinx: versal: Remove cortex-a53 compilation

Versal is a72 based that's why there is no reason to build low level
assemble code for a53.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: Iff9cf2582102d951825b87fd9af18e831ca717d6

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