Merge "driver: brcm: add USB driver" into integration

Merge "driver: brcm: add mdio driver" into integration

plat/arm: don't provide NT_FW_CONFIG when booting hafnium

NT_FW_CONFIG file is meant to be passed from BL31 to be consumed by
BL33, fvp platforms use this to pass measured boot configuration and
the

plat/arm: don't provide NT_FW_CONFIG when booting hafnium

NT_FW_CONFIG file is meant to be passed from BL31 to be consumed by
BL33, fvp platforms use this to pass measured boot configuration and
the x0 register is used to pass the base address of it.

In case of hafnium used as hypervisor in normal world, hypervisor
manifest is expected to be passed from BL31 and its base address is
passed in x0 register.

As only one of NT_FW_CONFIG or hypervisor manifest base address can be
passed in x0 register and also measured boot is not required for SPM so
disable passing NT_FW_CONFIG.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ifad9d3658f55ba7d70f468a88997d5272339e53e

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plat/st: do not keep mmc_device_info in stack

Create a dedicated static struct mmc_device_info mmc_info mmc_info
instead of having this in stack.
A boot issue has been seen on some platform when app

plat/st: do not keep mmc_device_info in stack

Create a dedicated static struct mmc_device_info mmc_info mmc_info
instead of having this in stack.
A boot issue has been seen on some platform when applying patch [1].

[1] 13f3c5166f1 ("mmc:prevent accessing to the released space in case of wrong usage")

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I73a079715253699d903721c865d6470d58f6bd30

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plat/intel: do not keep mmc_device_info in stack

Create a dedicated static struct mmc_device_info mmc_info mmc_info
instead of having this in stack.
A boot issue has been seen on some platform when

plat/intel: do not keep mmc_device_info in stack

Create a dedicated static struct mmc_device_info mmc_info mmc_info
instead of having this in stack.
A boot issue has been seen on some platform when applying patch [1].

[1] 13f3c5166f1 ("mmc:prevent accessing to the released space in case of wrong usage")

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Id52c0be61a30f453a551385883eaf3cbe32b04b9

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plat/hisilicon: do not keep mmc_device_info in stack

Create a dedicated static struct mmc_device_info mmc_info mmc_info
instead of having this in stack.
A boot issue has been seen on some platform w

plat/hisilicon: do not keep mmc_device_info in stack

Create a dedicated static struct mmc_device_info mmc_info mmc_info
instead of having this in stack.
A boot issue has been seen on some platform when applying patch [1].

[1] 13f3c5166f1 ("mmc:prevent accessing to the released space in case of wrong usage")

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: If5db8857cccec2e677b16a38eb3eeb41628a264c

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Merge changes from topic "my-topic-name" into integration

* changes:
plat: imx8mm: Add image load logic for TBBR FIP booting
plat: imx8mm: Add initial defintions to facilitate FIP layout
plat:

Merge changes from topic "my-topic-name" into integration

* changes:
plat: imx8mm: Add image load logic for TBBR FIP booting
plat: imx8mm: Add initial defintions to facilitate FIP layout
plat: imx8mm: Add image io-storage logic for TBBR FIP booting
plat: imx8mm: Add imx8mm_private.h to the build

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plat/arm/arm_image_load: refine plat_add_sp_images_load_info

Refine the function plat_add_sp_images_load_info() by saving the
previous node and only setting its next link when the current node is
va

plat/arm/arm_image_load: refine plat_add_sp_images_load_info

Refine the function plat_add_sp_images_load_info() by saving the
previous node and only setting its next link when the current node is
valid. This can reduce the check for the next node and simply the
total logic.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I4061428bf49ef0c3816ac22aaeb2e50315531f88

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plat/arm/arm_image_load: fix bug of overriding the last node

The traverse flow in function plat_add_sp_images_load_info() will find
the last node in the main load info list, with its
next_load_info=

plat/arm/arm_image_load: fix bug of overriding the last node

The traverse flow in function plat_add_sp_images_load_info() will find
the last node in the main load info list, with its
next_load_info==NULL. However this node is still useful and should not
be overridden with SP node info.

The bug will cause below error on RDN2 for spmd enabled:

ERROR: Invalid NT_FW_CONFIG DTB passed

Fix the bug by only setting the next_load_info of the last node in the
original main node list.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: Icaee5da1f2d53b29fdd6085a8cc507446186fd57

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plat:xilinx:versal: Add JTAG DCC support

As per the new multi-console framework, updating the JTAG DCC support.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Mic

plat:xilinx:versal: Add JTAG DCC support

As per the new multi-console framework, updating the JTAG DCC support.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I77994ce387caf0d695986df3d01d414a920978d0

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plat:xilinx:zynqmp: Add JTAG DCC support

As per the new multi-console framework, updating the JTAG DCC support.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Mic

plat:xilinx:zynqmp: Add JTAG DCC support

As per the new multi-console framework, updating the JTAG DCC support.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I62cfbb57ae7e454fbc91d1c54aafa6e99f9a35c8

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Add Cortex_A78C CPU lib

Add basic support for Cortex_A78C CPU.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Id9e41cbe0580a68c6412d194a5ee67940e8dae56

Merge changes from topic "allwinner_h616" into integration

* changes:
allwinner: H616: Add reserved-memory node to DT
allwinner: Add Allwinner H616 SoC support
allwinner: Add H616 SoC ID
all

Merge changes from topic "allwinner_h616" into integration

* changes:
allwinner: H616: Add reserved-memory node to DT
allwinner: Add Allwinner H616 SoC support
allwinner: Add H616 SoC ID
allwinner: Express memmap more dynamically
allwinner: Move sunxi_cpu_power_off_self() into platforms
allwinner: Move SEPARATE_NOBITS_REGION to platforms
doc: allwinner: Reorder sections, document memory mapping

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Merge "Add Makalu ELP CPU lib" into integration

Merge changes from topic "rd_updates" into integration

* changes:
plat/sgi: allow usage of secure partions on rdn2 platform
board/rdv1mc: initialize tzc400 controllers
plat/sgi: allow access t

Merge changes from topic "rd_updates" into integration

* changes:
plat/sgi: allow usage of secure partions on rdn2 platform
board/rdv1mc: initialize tzc400 controllers
plat/sgi: allow access to TZC controller on all chips
plat/sgi: define memory regions for multi-chip platforms
plat/sgi: allow access to nor2 flash and system registers from s-el0
plat/sgi: define default list of memory regions for dmc620 tzc
plat/sgi: improve macros defining cper buffer memory region
plat/sgi: refactor DMC-620 error handling SMC function id
plat/sgi: refactor SDEI specific macros

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plat/sgi: tag dmc620 MM communicate messages with a guid

Define a GUID that should be used in the header of MM communicate
message originating due to a dmc620 ECC error interrupt. So the use
of SMC

plat/sgi: tag dmc620 MM communicate messages with a guid

Define a GUID that should be used in the header of MM communicate
message originating due to a dmc620 ECC error interrupt. So the use
of SMC ID in 'sgi_ras_ev_map' to represent the interrupt event is
removed.

In addition to this, update the dmc620 error record data structure to
use aux_data to indicate the dmc620 instance number on which the ECC
error interrupt occurred.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I18c8ef5ba6483bb1bce6464ee9be0c2aabec4baa

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plat/sgi: allow usage of secure partions on rdn2 platform

Add the secure partition mmap table and the secure partition boot
information to support secure partitions on RD-N2 platform. In addition
to

plat/sgi: allow usage of secure partions on rdn2 platform

Add the secure partition mmap table and the secure partition boot
information to support secure partitions on RD-N2 platform. In addition
to this, add the required memory region mapping for accessing the
SoC peripherals from the secure partition.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I2c75760d6c8c3da3ff4885599be420e924aeaf3c

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Merge changes from topic "tzc400_stm32mp" into integration

* changes:
stm32mp1: add TZC400 interrupt management
stm32mp1: use TZC400 macro to describe filters
tzc400: add support for interrupts

board/rdv1mc: initialize tzc400 controllers

A TZC400 controller is placed inline on DRAM channels and regulates
the secure and non-secure accesses to both secure and non-secure
regions of the DRAM m

board/rdv1mc: initialize tzc400 controllers

A TZC400 controller is placed inline on DRAM channels and regulates
the secure and non-secure accesses to both secure and non-secure
regions of the DRAM memory. Configure each of the TZC controllers
across the Chips.

For use by secure software, configure the first chip's trustzone
controller to protect the upper 16MB of the memory of the first DRAM
block for secure accesses only. The other regions are configured for
non-secure read write access. For all the remote chips, all the DRAM
regions are allowed for non-secure read and write access.

Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I809f27eccadfc23ea0ef64e2fd87f95eb8f195c1

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plat/sgi: allow access to TZC controller on all chips

On a multi-chip platform, the boot CPU on the first chip programs the
TZC controllers on all the remote chips. Define a memory region map for
th

plat/sgi: allow access to TZC controller on all chips

On a multi-chip platform, the boot CPU on the first chip programs the
TZC controllers on all the remote chips. Define a memory region map for
the TZC controllers for all the remote chips and include it in the BL2
memory map table.

In addition to this, for SPM_MM enabled multi-chip platforms, increase
the number of mmap entries and xlat table counts for EL3 execution
context as well because the shared RAM regions and GIC address space of
remote chips are accessed.

Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I6f0b5fd22f9f28046451e382eef7f1f9258d88f7

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plat/sgi: define memory regions for multi-chip platforms

For multi-chip platforms, add a macro to define the memory regions on
chip numbers >1 and its associated access permissions. These memory
reg

plat/sgi: define memory regions for multi-chip platforms

For multi-chip platforms, add a macro to define the memory regions on
chip numbers >1 and its associated access permissions. These memory
regions are marked with non-secure access.

Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: If3d6180fd8ea61f45147c39d3140d694abf06617

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plat/sgi: allow access to nor2 flash and system registers from s-el0

Allow the access of system registers and nor2 flash memory region
from s-el0. This allows the secure parititions residing at s-el

plat/sgi: allow access to nor2 flash and system registers from s-el0

Allow the access of system registers and nor2 flash memory region
from s-el0. This allows the secure parititions residing at s-el0
to access these memory regions.

Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: I3887a86770de806323fbde0d20fdc96eec6e0c3c

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plat/sgi: define default list of memory regions for dmc620 tzc

Define a default DMC-620 TZC memory region configuration and use it to
specify the TZC memory regions on sgi575, rdn1edge and rde1edge

plat/sgi: define default list of memory regions for dmc620 tzc

Define a default DMC-620 TZC memory region configuration and use it to
specify the TZC memory regions on sgi575, rdn1edge and rde1edge
platforms. The default DMC-620 TZC memory regions are defined
considering the support for secure paritition as well.

Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: Iedee3e57d0d3de5b65321444da51ec990d3702db

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plat/sgi: improve macros defining cper buffer memory region

Remove the 'ARM_' prefix from the macros defining the CPER buffer memory
and replace it with 'CSS_SGI_' prefix. These macros are applicabl

plat/sgi: improve macros defining cper buffer memory region

Remove the 'ARM_' prefix from the macros defining the CPER buffer memory
and replace it with 'CSS_SGI_' prefix. These macros are applicable only
for platforms supported within plat/sgi. In addition to this, ensure
that these macros are defined only if the RAS_EXTENSION build option is
enabled.

Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: I44df42cded18d9d3a4cb13e5c990e9ab3194daee

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plat/sgi: refactor DMC-620 error handling SMC function id

The macros defining the SMC function ids for DMC-620 error handling are
listed in the sgi_base_platform_def.h header file. But these macros

plat/sgi: refactor DMC-620 error handling SMC function id

The macros defining the SMC function ids for DMC-620 error handling are
listed in the sgi_base_platform_def.h header file. But these macros are
not applicable for all platforms supported under plat/sgi. So move these
macro definitions to sgi_ras.c file in which these are consumed. While
at it, remove the AArch32 and error injection function ids as these are
unused.

Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: I249b54bf4c1b1694188a1e3b297345b942f16bc9

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