| 9ed4e6fb | 05-May-2021 |
Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> |
fix(plat/mediatek/pmic_wrap): update idle flow
Update idle flow in case of last read command timeout.
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: Idb0552d70d59b23822c
fix(plat/mediatek/pmic_wrap): update idle flow
Update idle flow in case of last read command timeout.
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: Idb0552d70d59b23822c38269d0fa9fe9ac0d6975
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|
| 8d4aa7d9 | 26-May-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "mt8192-apu" into integration
* changes:
feat(plat/mediatek/apu): add mt8192 APU device apc driver
feat(plat/mediatek/apu): add mt8192 APU SiP call support
feat(plat/m
Merge changes from topic "mt8192-apu" into integration
* changes:
feat(plat/mediatek/apu): add mt8192 APU device apc driver
feat(plat/mediatek/apu): add mt8192 APU SiP call support
feat(plat/mediatek/apu): add mt8192 APU iommap regions
feat(plat/mediatek/apu): setup mt8192 APU_S_S_4 and APU_S_S_5 permission
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| 3bb3157a | 26-May-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(plat/sgi): enable AMU for RD-V1-MC" into integration |
| f46e1f18 | 20-Apr-2021 |
Flora Fu <flora.fu@mediatek.com> |
feat(plat/mediatek/apu): add mt8192 APU device apc driver
Add APU device apc driver and setup permission.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: I2bbdb69d11267e4252b2138b5c5ac8f
feat(plat/mediatek/apu): add mt8192 APU device apc driver
Add APU device apc driver and setup permission.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: I2bbdb69d11267e4252b2138b5c5ac8faf752740f
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| ca4c0c2e | 20-Apr-2021 |
Flora Fu <flora.fu@mediatek.com> |
feat(plat/mediatek/apu): add mt8192 APU SiP call support
Add APU SiP call support for start/stop mcu.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: Ibf93d8ccf22c414de3093cee9e13f766858
feat(plat/mediatek/apu): add mt8192 APU SiP call support
Add APU SiP call support for start/stop mcu.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: Ibf93d8ccf22c414de3093cee9e13f7668588f69e
Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@mediatek.com>
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|
| 7eb42237 | 12-Apr-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(plat/mdeiatek/mt8195): add display port control in SiP service
MTK display port mute/unmute control registers need to be
set in secure world.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.c
feat(plat/mdeiatek/mt8195): add display port control in SiP service
MTK display port mute/unmute control registers need to be
set in secure world.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Iec73650e937bd20e25c18fa28d55ae29e68b10d3
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| e1e5b133 | 20-Apr-2021 |
Rajan Vaja <rajan.vaja@xilinx.com> |
fix(plat/xilinx/versal/include): correct IPI buffer offset
Use proper offset for IPI data based on offset for IPI0
channel.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Abhyuday
fix(plat/xilinx/versal/include): correct IPI buffer offset
Use proper offset for IPI data based on offset for IPI0
channel.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I3070517944dd353c3733aa595df0da030127751a
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| 2973dc5d | 18-Nov-2020 |
Jeremy Linton <jeremy.linton@arm.com> |
rpi4: update the iobase constant
The PCIe root port is outside of the current RPi
MMIO regions, so we need to adjust the address map.
Given much of the code depends on the legacy IOBASE
lets separat
rpi4: update the iobase constant
The PCIe root port is outside of the current RPi
MMIO regions, so we need to adjust the address map.
Given much of the code depends on the legacy IOBASE
lets separate that from the actual MMIO begin/end.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Change-Id: Id65460ae58556bd8826dba08bbad79953e2a7c0b
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| 2671f318 | 20-Apr-2021 |
Flora Fu <flora.fu@mediatek.com> |
feat(plat/mediatek/apu): add mt8192 APU iommap regions
Add APU iommap settings for reviser, apu_ao and
devapc control wrapper.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: Ie8e6a197c0
feat(plat/mediatek/apu): add mt8192 APU iommap regions
Add APU iommap settings for reviser, apu_ao and
devapc control wrapper.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: Ie8e6a197c0f440f9e4ee8101202283a2dbf501a6
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| 77b68019 | 20-Apr-2021 |
Flora Fu <flora.fu@mediatek.com> |
feat(plat/mediatek/apu): setup mt8192 APU_S_S_4 and APU_S_S_5 permission
Setup APU_S_S_4/APU_S_S_5 permission as SEC_RW_ONLY.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: I6c50b2913bf
feat(plat/mediatek/apu): setup mt8192 APU_S_S_4 and APU_S_S_5 permission
Setup APU_S_S_4/APU_S_S_5 permission as SEC_RW_ONLY.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: I6c50b2913bf34270a1b0ffaf0e0c435fee192a4c
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|
| 09e153a9 | 24-May-2021 |
Mark Dykes <mark.dykes@arm.com> |
Merge "feat(hw_crc): add support for HW computed CRC" into integration |
| 9ce232fe | 10-Mar-2021 |
Igor Opaniuk <igor.opaniuk@foundries.io> |
feat(plat/imx8m): add SiP call for secondary boot
In iMX8MM it is possible to have two copies of bootloader in
SD/eMMC and switch between them. The switch is triggered either
by the BootROM in case
feat(plat/imx8m): add SiP call for secondary boot
In iMX8MM it is possible to have two copies of bootloader in
SD/eMMC and switch between them. The switch is triggered either
by the BootROM in case the bootloader image is faulty OR can be
enforced by the user. To trigger that switch the
PERSIST_SECONDARY_BOOT bit should be set in GPR10 SRC register.
As the bit is retained after WARM reset, that permits to control
BootROM behavior regarding what boot image it will boot after
reset: primary or secondary.
This is useful for reliable bootloader A/B updates, as it permits
switching between two copies of bootloader at different offsets of
the same storage.
If the PERSIST_SECONDARY_BOOT is 0, the boot ROM uses address
0x8400 for the primary image. If the PERSIST_SECONDARY_BOOT is 1,
the boot ROM reads that secondary image table from address 0x8200
on the boot media and uses the address specified in the table for
the secondary image.
Secondary Image Table contains the sector of secondary bootloader
image, exluding the offset to that image (explained below in the
note). To generate the Secondary Image Table, use e.g.:
$ printf '\x0\x0\x0\x0\x0\x0\x0\x0\x33\x22\x11'
'\x00\x00\x10\x0\x0\x00\x0\x0\x0'
> /tmp/sit.bin
$ hexdump -vC /tmp/sit.bin
00000000 00 00 00 00
00000004 00 00 00 00
00000008 33 22 11 00 <--- This is the "tag"
0000000c 00 10 00 00 <--- This is the "firstSectorNumber"
00000010 00 00 00 00
You can also use NXP script from [1][2] imx-mkimage tool for
SIT generation. Note that the firstSectorNumber is NOT the offset
of the IVT, but an offset of the IVT decremented by Image Vector
Table offset (Table 6-25. Image Vector Table Offset and Initial
Load Region Size for iMX8MM/MQ), so for secondary SPL copy at
offset 0x1042 sectors, firstSectorNumber must be 0x1000
(0x42 sectors * 512 = 0x8400 bytes offset).
In order to test redundant boot board should be closed and
SD/MMC manufacture mode disabled, as secondary boot is not
supported in the SD/MMC manufacture mode, which can be disabled
by blowing DISABLE_SDMMC_MFG (example for iMX8MM):
> fuse prog -y 2 1 0x00800000
For additional details check i.MX 8M Mini Apllication Processor
Reference Manual, 6.1.5.4.5 Redundant boot support for
expansion device chapter.
[1] https://source.codeaurora.org/external/imx/imx-mkimage/
[2] scripts/gen_sit.sh
Change-Id: I0a5cea7295a4197f6c89183d74b4011cada52d4c
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
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|
| a1cedadf | 22-Apr-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(hw_crc): add support for HW computed CRC
Added support for HW computed CRC using Arm ACLE intrinsics.
These are built-in intrinsics available for ARMv8.1-A, and
onwards.
These intrinsics are en
feat(hw_crc): add support for HW computed CRC
Added support for HW computed CRC using Arm ACLE intrinsics.
These are built-in intrinsics available for ARMv8.1-A, and
onwards.
These intrinsics are enabled via '-march=armv8-a+crc' compile
switch for ARMv8-A (supports CRC instructions optionally).
HW CRC support is enabled unconditionally in BL2 for all Arm
platforms.
HW CRC calculation is verified offline to ensure a similar
result as its respective ZLib utility function.
HW CRC calculation support will be used in the upcoming
firmware update patches.
Change-Id: Ia2ae801f62d2003e89a9c3e6d77469b5312614b3
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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|
| 63ca6bba | 13-May-2021 |
Zelalem <zelalem.aweke@arm.com> |
refactor(juno): disable non-invasive debug of secure state
Disable non-invasive debug of secure state for Juno
in release builds. This makes sure that PMU counts
only Non-secure events.
Signed-off-
refactor(juno): disable non-invasive debug of secure state
Disable non-invasive debug of secure state for Juno
in release builds. This makes sure that PMU counts
only Non-secure events.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I0d1c3f96f3b4e48360a7211ae55851d65d291025
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|
| ca932481 | 10-Mar-2021 |
Davidson K <davidson.kumaresan@arm.com> |
feat(tc0): add support for trusted services
This patch adds support for the crypto and secure storage secure
partitions for the Total Compute platform. These secure partitions
have to be managed by
feat(tc0): add support for trusted services
This patch adds support for the crypto and secure storage secure
partitions for the Total Compute platform. These secure partitions
have to be managed by Hafnium executing at S-EL2
Change-Id: I2df690e3a99bf6bf50e2710994a905914a07026e
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
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| e8b119e0 | 23-Mar-2021 |
Pranav Madhu <pranav.madhu@arm.com> |
feat(plat/sgi): enable AMU for RD-V1-MC
AMU counters are used for monitoring the CPU performance. RD-V1-MC
platform has architected AMU available for each core. Enable the use of
AMU by non-secure O
feat(plat/sgi): enable AMU for RD-V1-MC
AMU counters are used for monitoring the CPU performance. RD-V1-MC
platform has architected AMU available for each core. Enable the use of
AMU by non-secure OS for supporting the use of counters for processor
performance control (ACPI CPPC).
Change-Id: I33be594cee669e7f4031e5e5a371eec7c7451030
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
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| 44de593d | 30-Apr-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "plat/st: do not rely on tainted value for dt property length" into integration |
| 7f9390d3 | 22-Oct-2020 |
Jacky Bai <ping.bai@nxp.com> |
plat: imx8mp: change the bl31 physical load address
on i.MX8MP A1 silicon, the OCRAM space is extended to 512K + 64K,
currently, OCRAM @0x960000-0x980000 is reserved for BL31, it will
leave the last
plat: imx8mp: change the bl31 physical load address
on i.MX8MP A1 silicon, the OCRAM space is extended to 512K + 64K,
currently, OCRAM @0x960000-0x980000 is reserved for BL31, it will
leave the last 64KB in non-continuous space. To provide a continuous
384KB + 64KB space for generic use, so move the BL31 space to
0x970000-0x990000 range.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I96d572fc0f87f05a60f55e0552a68b6e70f8e7f4
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| 8c72a7ab | 11-Aug-2020 |
Jacky Bai <ping.bai@nxp.com> |
plat: imx8m: Fix the macro define error
the 'always_on' member should be initialized from 'on'.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I5746ff40075b4fcda2ac7d04a8d7f1269af17e91 |
| dd6efc9e | 30-Apr-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I8e67a921,I0dc06072,I5e149063,I962cdfc7,I5c5d0444 into integration
* changes:
plat: ti: k3: board: Let explicitly map our SEC_SRAM_BASE to 0x0
plat: ti: k3: board: Lets cast our ma
Merge changes I8e67a921,I0dc06072,I5e149063,I962cdfc7,I5c5d0444 into integration
* changes:
plat: ti: k3: board: Let explicitly map our SEC_SRAM_BASE to 0x0
plat: ti: k3: board: Lets cast our macros
plat: ti: k3: common: bl31_setup: Use BL31_SIZE instead of computing
plat: ti: k3: platform_def.h: Define the correct number of max table entries
plat: ti: k3: board: lite: Increase SRAM size to account for additional table
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| f714ca80 | 10-Mar-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
plat/st: do not rely on tainted value for dt property length
To compare the "okay" string of a property, strncmp is used but with the
length given by fdt_getprop. This len value is reported as taint
plat/st: do not rely on tainted value for dt property length
To compare the "okay" string of a property, strncmp is used but with the
length given by fdt_getprop. This len value is reported as tainted by
Coverity [1]. We just can use strlen("okay") which is a known value
to compare the 2 strings.
[1] https://scan4.coverity.com/reports.htm#v51972/p11439/fileInstanceId=96515154&defectInstanceId=14219121&mergedDefectId=342997
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ic8fb6ccf3126a37df615e433eb028861812015da
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| 6794378d | 29-Apr-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "fw-update" into integration
* changes:
docs: add build options for GPT support enablement
feat(plat/arm): add GPT parser support |
| 08e7cc53 | 29-Apr-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I15e7cc43,Id7411bd5,I92bafe70,I8f1c0658 into integration
* changes:
stm32mp1: enable PIE for BL32
stm32mp1: set BL sizes regardless of flags
Add PIE support for AARCH32
Avoid t
Merge changes I15e7cc43,Id7411bd5,I92bafe70,I8f1c0658 into integration
* changes:
stm32mp1: enable PIE for BL32
stm32mp1: set BL sizes regardless of flags
Add PIE support for AARCH32
Avoid the use of linker *_SIZE__ macros
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|
| ef1daa42 | 22-Feb-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(plat/arm): add GPT parser support
Added GPT parser support in BL2 for Arm platforms to get the entry
address and length of the FIP in the GPT image.
Also, increased BL2 maximum size for FVP pl
feat(plat/arm): add GPT parser support
Added GPT parser support in BL2 for Arm platforms to get the entry
address and length of the FIP in the GPT image.
Also, increased BL2 maximum size for FVP platform to successfully
compile ROM-enabled build with this change.
Verified this change using a patch:
https://review.trustedfirmware.org/c/ci/tf-a-ci-scripts/+/9654
Change-Id: Ie8026db054966653b739a82d9ba106d283f534d0
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 800b8849 | 28-Apr-2021 |
Mark Dykes <mark.dykes@arm.com> |
Merge "refactor(plat/arm): replace FIP base and size macro with a generic name" into integration |