Merge "fix(plat/qemu): (NS_DRAM0_BASE + NS_DRAM0_SIZE) ADDR overflow 32bit" into integration

Merge "fix(plat/st): apply security at the end of BL2" into integration

refactor(gicv3): rename GIC Clayton to GIC-700

The GIC IP formerly known as "GIC Clayton" has been released under the
name of "GIC-700".

Rename occurences of Clayton in comments and macro names to

refactor(gicv3): rename GIC Clayton to GIC-700

The GIC IP formerly known as "GIC Clayton" has been released under the
name of "GIC-700".

Rename occurences of Clayton in comments and macro names to reflect the
official name.

Change-Id: Ie8c55f7da7753127d58c8382b0033c1b486f7909
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "fix(plat/arm_fpga): enable AMU extension" into integration

feat(plat/xilinx/zynqmp): add support for runtime feature config

Add support for runtime feature configuration which are running on the
firmware. Add new IOCTL IDs like IOCTL_SET_FEATURE_CONFIG and

feat(plat/xilinx/zynqmp): add support for runtime feature config

Add support for runtime feature configuration which are running on the
firmware. Add new IOCTL IDs like IOCTL_SET_FEATURE_CONFIG and
IOCTL_GET_FEATURE_CONFIG for configuring the features.

Signed-off-by: Ronak Jain <ronak.jain@xilinx.com>
Change-Id: I976aef15932783a25396b2adeb4c8f140cc87e79

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feat(plat/xilinx/zynqmp): sync IOCTL IDs

Sync IOCTL IDs in order to avoid conflict with other components like,
Linux and firmware. Hence assigning value to IDs to make it more
specific.

Signed-of

feat(plat/xilinx/zynqmp): sync IOCTL IDs

Sync IOCTL IDs in order to avoid conflict with other components like,
Linux and firmware. Hence assigning value to IDs to make it more
specific.

Signed-off-by: Ronak Jain <ronak.jain@xilinx.com>
Change-Id: I11ae679fbd0a953290306b62d661cc142f50dc28

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fix(plat/qemu): (NS_DRAM0_BASE + NS_DRAM0_SIZE) ADDR overflow 32bit

after this commit: If15cf3b9d3e2e7876c40ce888f22e887893fe696
plat/qemu/common/qemu_pm.c:116: (entrypoint < (NS_DRAM0_BASE + NS

fix(plat/qemu): (NS_DRAM0_BASE + NS_DRAM0_SIZE) ADDR overflow 32bit

after this commit: If15cf3b9d3e2e7876c40ce888f22e887893fe696
plat/qemu/common/qemu_pm.c:116: (entrypoint < (NS_DRAM0_BASE + NS_DRAM0_SIZE)))
the above line (NS_DRAM0_BASE + NS_DRAM0_SIZE) = 0x100000000, which will
overflow 32bit and cause ERROR
SO add ULL to fix it

tested on compiler:
gcc version 10.2.1 20201103 (GNU Toolchain for the A-profile Architecture 10.2-2020.11 (arm-10.16))

Signed-off-by: Darren Liang <lwp513@qq.com>
Change-Id: I1d769b0803142d37bd2968d765ab04a9c7c5c21a

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Merge "feat: enabling stack protector for diphda" into integration

cpu: add support for Demeter CPU

This patch adds the basic CPU library code to support the Demeter
CPU. This CPU is based on the Makalu-ELP core so that CPU lib code
was adapted to create this patc

cpu: add support for Demeter CPU

This patch adds the basic CPU library code to support the Demeter
CPU. This CPU is based on the Makalu-ELP core so that CPU lib code
was adapted to create this patch.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ib5740b748008a72788c557f0654d8d5e9ec0bb7f

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fix(plat/arm_fpga): enable AMU extension

As done recently for plat/tc0 in b5863cab9, enable AMU explicitly.
This is necessary as the recent changes that enable SVE for the secure
world disable AMU b

fix(plat/arm_fpga): enable AMU extension

As done recently for plat/tc0 in b5863cab9, enable AMU explicitly.
This is necessary as the recent changes that enable SVE for the secure
world disable AMU by default in the CPTR_EL3 reset value.

Change-Id: Ie3abf1dee8a4e1c8c39f934da8e32d67891f5f09
Signed-off-by: Tom Cosgrove <tom.cosgrove@arm.com>

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fix(plat/st): apply security at the end of BL2

Now that the DDR is mapped secured, the security settings (TZC400
firewall) have to be applied at the end of BL2 for the OP-TEE case.
This is required

fix(plat/st): apply security at the end of BL2

Now that the DDR is mapped secured, the security settings (TZC400
firewall) have to be applied at the end of BL2 for the OP-TEE case.
This is required to avoid checskum computation error on U-Boot binary,
for which MMU and TZC400 would not be aligned.

Change-Id: I4a364f7117960e8fae1b579f341b9f140b766ea6
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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refactor(tegra132): deprecate platform

The Tegra132 platforms have reached their end of life and are
no longer used in the field. Internally and externally, all
known programs have removed support f

refactor(tegra132): deprecate platform

The Tegra132 platforms have reached their end of life and are
no longer used in the field. Internally and externally, all
known programs have removed support for this legacy platform.

This change removes this platform from the Tegra tree as a result.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I72edb689293e23b63290cdcaef60468b90687a5a

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fix(rpi4): drop /memreserve/ region

Most DTBs used on the RaspberryPi contain a FDT /memreserve/ region,
that covers the original secondaries' spin table.
We need to reserve more memory than describ

fix(rpi4): drop /memreserve/ region

Most DTBs used on the RaspberryPi contain a FDT /memreserve/ region,
that covers the original secondaries' spin table.
We need to reserve more memory than described there, to cover the whole
of the TF-A image, so we add a /reserved-memory node to the DTB.

However having the same memory region described by both methods upsets
the Linux kernel and U-Boot, so we have to make sure there is only one
instance describing this reserved memory.

Keep our currently used /reserved-memory node, since it's more capable
(it allows to mark the region as secure memory). Add some code to drop
the original /memreserve/ region, since we don't need this anymore,
because we take the secondaries out of their original spin loop.

We explicitly check for the currently used size of 4KB for this region,
to be alerted by any changes to this region in the upstream DTB.

Change-Id: Ia3105560deb3f939e026f6ed715a9bbe68b56230
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "refactor(plat/ea_handler): Use default ea handler implementation for panic" into integration

Merge "feat(plat/versal): add support for SLS mitigation" into integration

refactor(plat/ea_handler): Use default ea handler implementation for panic

Put default ea handler implementation into function plat_default_ea_handler()
which just print verbose information and pani

refactor(plat/ea_handler): Use default ea handler implementation for panic

Put default ea handler implementation into function plat_default_ea_handler()
which just print verbose information and panic, so it can be called also
from overwritten / weak function plat_ea_handler() implementation.

Replace every custom implementation of printing verbose error message of
external aborts in custom plat_ea_handler() functions by a common
implementation from plat_default_ea_handler() function.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I15897f61b62b4c3c29351e693f51d4df381f3b98

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Merge changes Id93c4573,Ib7fea862,I44b9e5a9,I9e0ef734,I94d550ce, ... into integration

* changes:
feat(plat/rcar3): emit RPC status to DT fragment if RPC unlocked
feat(plat/rcar3): add a DRAM siz

Merge changes Id93c4573,Ib7fea862,I44b9e5a9,I9e0ef734,I94d550ce, ... into integration

* changes:
feat(plat/rcar3): emit RPC status to DT fragment if RPC unlocked
feat(plat/rcar3): add a DRAM size setting for M3N
feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.0
feat(plat/rcar3): add new board revision for Salvator-XS/H3ULCB
feat(drivers/rcar3): ddr: add function to judge a DDR rank
fix(drivers/rcar3): ddr: update DDR setting for H3, M3, M3N
fix(drivers/rcar3): i2c_dvfs: fix I2C operation
fix(drivers/rcar3): fix CPG registers redefinition
fix(drivers/rcar3): emmc: remove CPG_CPGWPR redefinition
fix(plat/rcar3): generate two memory nodes for larger than 2 GiB channel 0
refactor(plat/rcar3): factor out DT memory node generation
feat(plat/rcar3): add optional support for gzip-compressed BL33

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Merge changes from topic "st_fip_fconf" into integration

* changes:
feat(io_mtd): offset management for FIP usage
feat(nand): count bad blocks before a given offset
feat(plat/st): add helper t

Merge changes from topic "st_fip_fconf" into integration

* changes:
feat(io_mtd): offset management for FIP usage
feat(nand): count bad blocks before a given offset
feat(plat/st): add helper to save boot interface
fix(plat/st): improve DDR get size function
refactor(plat/st): map DDR secure at boot
refactor(plat/st): rework TZC400 configuration

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feat: enabling stack protector for diphda

This commit activates the stack protector feature for the diphda
platform.

Change-Id: Ib16b74871c62b67e593a76ecc12cd3634d212614
Signed-off-by: Abdellatif E

feat: enabling stack protector for diphda

This commit activates the stack protector feature for the diphda
platform.

Change-Id: Ib16b74871c62b67e593a76ecc12cd3634d212614
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>

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Merge "feat(plat/imx/imx8m/imx8mm): enlarge BL33 (U-boot) size in FIP" into integration

feat(plat/arm): Introduce TC1 platform

This renames tc0 platform folder and files to tc, and introduces
TARGET_PLATFORM variable to account for the differences between
TC0 and TC1.

Signed-off-by: U

feat(plat/arm): Introduce TC1 platform

This renames tc0 platform folder and files to tc, and introduces
TARGET_PLATFORM variable to account for the differences between
TC0 and TC1.

Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I5b4a83f3453afd12542267091b3edab4c139c5cd

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Merge "feat(plat/mdeiatek/mt8192): add DFD control in SiP service" into integration

Merge "revert(plat/xilinx): add timeout while waiting for IPI Ack" into integration

Merge "feat(ff-a): update FF-A version to v1.1" into integration

revert(plat/xilinx): add timeout while waiting for IPI Ack

This reverts commit 4d9b9b2352f9a67849faf2d4484f5fcdd2788b01.

Timeout in IPI ack was added for functional safety reason.
Functional safety

revert(plat/xilinx): add timeout while waiting for IPI Ack

This reverts commit 4d9b9b2352f9a67849faf2d4484f5fcdd2788b01.

Timeout in IPI ack was added for functional safety reason.
Functional safety is not criteria for ATF. However, this
creates issues for APIs that take long or non-deterministic
duration like FPGA load. So revert this patch for now to fix
FPGA loading issue. Need to add support for non-blocking API
for FPGA loading with callback when API completes.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I940e798f1e2f7d0dfca1da5caaf8b94036d440c6

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