feat(plat/nxp/common/psci): define CPUECTLR_TIMER_2TICKS

Define CPUECTLR_TIMER_2TICKS.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Iecb5ed

feat(plat/nxp/common/psci): define CPUECTLR_TIMER_2TICKS

Define CPUECTLR_TIMER_2TICKS.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Iecb5ede82939e8502d2f1bc74ec3bfe2a00be65c

show more ...

feat(plat/nxp/common): define default PSCI features if not defined

SoC code can define supported features, otherwise use default setting.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: J

feat(plat/nxp/common): define default PSCI features if not defined

SoC code can define supported features, otherwise use default setting.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I0f11498c1f7558ff0ec2d9b344f3f7a4f5489ced

show more ...

feat(plat/nxp/common): define common macro for ARM registers

Define common register macro both for Cortex-A53 and Cortex-A72
because the code will be used by both Cortex platform.

Signed-off-by: Bi

feat(plat/nxp/common): define common macro for ARM registers

Define common register macro both for Cortex-A53 and Cortex-A72
because the code will be used by both Cortex platform.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I485661bfe3ed4f214c403ff6af53dc6af1ddf089

show more ...

feat(plat/nxp/common): add CCI and EPU address definition

Add CCI and EPU base address definiton for Chassis v3.2.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I13250555b6646c1e7ba2e9d

feat(plat/nxp/common): add CCI and EPU address definition

Add CCI and EPU base address definiton for Chassis v3.2.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I13250555b6646c1e7ba2e9d7c9efca8501f17b3a

show more ...

feat(plat/mediatek/mt8195): add EMI MPU basic drivers

EMI MPU stands for external memory interface memory protect unit.
MT8195 supports 32 regions and 16 domains.
We add basic drivers currently, and

feat(plat/mediatek/mt8195): add EMI MPU basic drivers

EMI MPU stands for external memory interface memory protect unit.
MT8195 supports 32 regions and 16 domains.
We add basic drivers currently, and will add more setting for
EMI MPU in next patch.

Change-Id: Iedc19d8f6fcf1ceb2d8241319b8dc17c885642dd
Signed-off-by: Penny Jan <penny.jan@mediatek.com>

show more ...

Merge "fix(plat/synquacer): update scmi power domain off handling" into integration

feat(plat/imx/imx8m/imx8mp): enable Trusted Boot

This patch enables Trusted Boot on the i.MX8MP with BL2 doing image
verification from a FIP prior to hand-over to BL31.

Signed-off-by: Ying-Chun Liu

feat(plat/imx/imx8m/imx8mp): enable Trusted Boot

This patch enables Trusted Boot on the i.MX8MP with BL2 doing image
verification from a FIP prior to hand-over to BL31.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: Iac1d1d62ea9858f67326a47c1e5ba377f23f9db5

show more ...

feat(plat/imx/imx8m/imx8mp): add in BL2 with FIP

Adds bl2 with FIP to the build required for mbed Linux booting where
we do:

BootROM -> SPL -> BL2 -> OPTEE -> u-boot

If NEED_BL2 is specified then

feat(plat/imx/imx8m/imx8mp): add in BL2 with FIP

Adds bl2 with FIP to the build required for mbed Linux booting where
we do:

BootROM -> SPL -> BL2 -> OPTEE -> u-boot

If NEED_BL2 is specified then BL2 will be built and BL31 will have its
address range modified upwards to accommodate. BL31 must be loaded from a
FIP in this case.

If NEED_BL2 is not specified then the current BL31 boot flow is unaffected
and u-boot SPL will load and execute BL31 directly.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I78914d6002755f733ea866127cb47982a00f9700

show more ...

refactor(plat/imx/imx8m): make image load logic for TBBR FIP booting common

This commit makes the image load logic from imx8mm common for all
imx8m platform.

Signed-off-by: Ying-Chun Liu (PaulLiu)

refactor(plat/imx/imx8m): make image load logic for TBBR FIP booting common

This commit makes the image load logic from imx8mm common for all
imx8m platform.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: Ibfe2e9cc09d198cb9e309afaf381a0237a4b82ed

show more ...

feat(plat/imx/imx8m/imx8mp): add initial definition to facilitate FIP layout

Adds a number of definitions consistent with the established RSB3720
equivalents specifying number of io_handles and bloc

feat(plat/imx/imx8m/imx8mp): add initial definition to facilitate FIP layout

Adds a number of definitions consistent with the established RSB3720
equivalents specifying number of io_handles and block devices.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I401e48216d67257137351ee4d0b98904a76fa789

show more ...

refactor(plat/imx/imx): make imx io-storage logic for TBBR/FIP common

This commit makes imx image io-storage logic common for all
imx platform.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debia

refactor(plat/imx/imx): make imx io-storage logic for TBBR/FIP common

This commit makes imx image io-storage logic common for all
imx platform.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I15045ac8f9dfa8cb714e32f9e7475d5eae4e86e4

show more ...

feat(plat/imx/imx8m/imx8mp): add imx8mp_private.h to the build

Allows for exporting of FIP related methods cleanly in a private header.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
C

feat(plat/imx/imx8m/imx8mp): add imx8mp_private.h to the build

Allows for exporting of FIP related methods cleanly in a private header.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: Iaaad4e69ef89c8a8a74648647d7fd09cd0fdd12a

show more ...

fix(plat/synquacer): update scmi power domain off handling

In the SCMI power domain off handling, configure GIC
to prevent interrupt toward to the core to be turned off,
and configure CCN to disable

fix(plat/synquacer): update scmi power domain off handling

In the SCMI power domain off handling, configure GIC
to prevent interrupt toward to the core to be turned off,
and configure CCN to disable coherency when the cluster is turned off.
The same operation is done in SCPI power domain off processing.

This commit adds the missing operation in SCMI power domain
off handling.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: Ib3523de488500c2e8bdc74e4cb8772a1442d9781

show more ...

feat(plat/mediatek/mt8195): add vcore-dvfs support

Add DVFSRC init flow.

Change-Id: Ic5fc78c91359abc12c0f54b01860a7cbe41f3358
Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>

Merge "fix(plat/qti/sc7180): qti smc addition" into integration

feat(plat/rcar3): keep RWDT enabled

In case the WDT is enabled by prior stage, keep it enabled.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ie7c0eaf2f59dd8c30a9ef686a70004

feat(plat/rcar3): keep RWDT enabled

In case the WDT is enabled by prior stage, keep it enabled.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ie7c0eaf2f59dd8c30a9ef686a7000424f38d6352

show more ...

feat(plat/rcar3): modify LifeC register setting for R-Car D3

Modified SECGRP0COND6 and SECGRP1COND6 setting for R-Car D3.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by

feat(plat/rcar3): modify LifeC register setting for R-Car D3

Modified SECGRP0COND6 and SECGRP1COND6 setting for R-Car D3.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I3f173ac44c11743965c013ef238748b0dc8cabab

show more ...

feat(plat/rcar3): remove access to RMSTPCRn registers in R-Car D3

Because the Realtime module stop control register n (RMSTPCRn)
are not supported in R-Car D3. Therefore, remove access to these
regi

feat(plat/rcar3): remove access to RMSTPCRn registers in R-Car D3

Because the Realtime module stop control register n (RMSTPCRn)
are not supported in R-Car D3. Therefore, remove access to these
registers in R-Car D3.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I4647e28d0e176ff97151e9842019ba12cefe5c03

show more ...

feat(plat/rcar3): add process of SSCG setting for R-Car D3

- Added the condition where output the SSCG (MD12) setting
to log for R-Car D3.
- Added the process to switching the bit rate of SCIF by

feat(plat/rcar3): add process of SSCG setting for R-Car D3

- Added the condition where output the SSCG (MD12) setting
to log for R-Car D3.
- Added the process to switching the bit rate of SCIF by the
SSCG (MD12) setting value for R-Car D3.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Iaf07fa4df12dc233af0b57569ee4fa9329f670a9

show more ...

feat(plat/rcar3): add process to back up X6 and X7 register's value

Because the x6 and x7 registers will be overwritten by the callee function,
added the processing the register's value push to/pop

feat(plat/rcar3): add process to back up X6 and X7 register's value

Because the x6 and x7 registers will be overwritten by the callee function,
added the processing the register's value push to/pop from stack memory.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I5351a008d3b208a30a8bc8651b8d9b4d1a02a8e8

show more ...

feat(plat/rcar3): add SYSCEXTMASK bit set/clear in scu_power_up

Added the process of SYSECEXTMASK bit set/clear for following
power Resume/Shutoff flow.

Signed-off-by: Hideyuki Nitta <hideyuki.nitt

feat(plat/rcar3): add SYSCEXTMASK bit set/clear in scu_power_up

Added the process of SYSECEXTMASK bit set/clear for following
power Resume/Shutoff flow.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I71ed22840a42e7ab7d87bfd4241eec6f5ddb129b

show more ...

feat(plat/rcar3): change the memory map for OP-TEE

The memory area size of OP-TEE was changed from 1MB to 2MB
because the size of OP-TEE has increased.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki

feat(plat/rcar3): change the memory map for OP-TEE

The memory area size of OP-TEE was changed from 1MB to 2MB
because the size of OP-TEE has increased.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Ic8a165c83a3a9ef2829f68d5fabeed9ccb6da95e

show more ...

feat(plat/rcar3): use PRR cut to determine DRAM size on M3

The new M3 DRAM size can be determined by the PRR cut version.
Read the PRR cut version, and if it is older than cut 30, use
legacy DRAM si

feat(plat/rcar3): use PRR cut to determine DRAM size on M3

The new M3 DRAM size can be determined by the PRR cut version.
Read the PRR cut version, and if it is older than cut 30, use
legacy DRAM size scheme, else report 8GB in 2GBx4 2ch split.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # Fix DRAM size judgment by PRR register, reword commit message
Change-Id: Ib83176d0d09cab5cae0119ba462e42c66c642798

show more ...

feat(plat/rcar3): apply ERRATA_A53_1530924 and ERRATA_A57_1319537

Apply ERRATA_A53_1530924 and ERRATA_A57_1319537.

Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: T

feat(plat/rcar3): apply ERRATA_A53_1530924 and ERRATA_A57_1319537

Apply ERRATA_A53_1530924 and ERRATA_A57_1319537.

Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # Drop Makefile header change, reword commit message
Change-Id: I7d6e7e40bad6545a1d96470ce1a6e2d04e042670

show more ...

fix(plat/rcar3): fix disabling MFIS write protection for R-Car D3

Fix disabling MFIS write protection for R-Car D3.

Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by:

fix(plat/rcar3): fix disabling MFIS write protection for R-Car D3

Fix disabling MFIS write protection for R-Car D3.

Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I8bb5787c09c53dff55d6de89adfcb71157533976

show more ...